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@ -32,6 +32,8 @@ CPU::CPU(uint32_t frequency) |
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, m_hf(0x0) |
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, m_hf(0x0) |
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, m_cf(0x0) |
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, m_cf(0x0) |
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{ |
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{ |
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// FIXME: Figure out if other ProcessingUnits require access to these registers,
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// delete this functionality if they dont
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m_shared_registers.emplace("a", &m_a); |
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m_shared_registers.emplace("a", &m_a); |
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m_shared_registers.emplace("b", &m_b); |
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m_shared_registers.emplace("b", &m_b); |
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m_shared_registers.emplace("c", &m_c); |
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m_shared_registers.emplace("c", &m_c); |
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@ -57,6 +59,9 @@ void CPU::update() |
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{ |
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{ |
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m_wait_cycles--; |
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m_wait_cycles--; |
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if (m_wait_cycles <= 0) { |
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if (m_wait_cycles <= 0) { |
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// print(ruc::format::Emphasis::Underline | ruc::format::Emphasis::Bold | fg(ruc::format::TerminalColor::Blue), "{:#06x}\n", *this);
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// Read next opcode
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// Read next opcode
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uint8_t opcode = read(m_pc); |
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uint8_t opcode = read(m_pc); |
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print("running opcode: {:#x}\n", opcode); |
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print("running opcode: {:#x}\n", opcode); |
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@ -98,6 +103,7 @@ void CPU::update() |
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default: |
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default: |
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print("opcode {:#x} not implemented\n", opcode); |
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print("opcode {:#x} not implemented\n", opcode); |
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print("pc: {:#x}, immediate: {:#x}\n", m_pc, pcRead()); |
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VERIFY_NOT_REACHED(); |
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VERIFY_NOT_REACHED(); |
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} |
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} |
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} |
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} |
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