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@ -257,21 +257,25 @@ void CPU::update() |
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case 0xbe: cp(); break; |
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case 0xbe: cp(); break; |
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case 0xbf: cp(); break; |
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case 0xbf: cp(); break; |
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case 0xc1: pop(); break; |
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case 0xc1: pop(); break; |
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case 0xc2: jp16(); break; |
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case 0xc3: jp16(); break; |
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case 0xc3: jp16(); break; |
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case 0xc4: call(); break; |
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case 0xc4: call(); break; |
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case 0xc5: push(); break; |
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case 0xc5: push(); break; |
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case 0xc6: add8(); break; |
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case 0xc6: add8(); break; |
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case 0xc7: rst(); break; |
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case 0xc7: rst(); break; |
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case 0xca: jp16(); break; |
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case 0xcb: prefix(); break; |
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case 0xcb: prefix(); break; |
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case 0xcc: call(); break; |
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case 0xcc: call(); break; |
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case 0xcd: call(); break; |
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case 0xcd: call(); break; |
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case 0xce: adc8(); break; |
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case 0xce: adc8(); break; |
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case 0xcf: rst(); break; |
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case 0xcf: rst(); break; |
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case 0xd1: pop(); break; |
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case 0xd1: pop(); break; |
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case 0xd2: jp16(); break; |
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case 0xd4: call(); break; |
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case 0xd4: call(); break; |
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case 0xd5: push(); break; |
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case 0xd5: push(); break; |
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case 0xd6: sub8(); break; |
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case 0xd6: sub8(); break; |
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case 0xd7: rst(); break; |
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case 0xd7: rst(); break; |
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case 0xda: jp16(); break; |
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case 0xdc: call(); break; |
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case 0xdc: call(); break; |
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case 0xde: sbc8(); break; |
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case 0xde: sbc8(); break; |
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case 0xdf: rst(); break; |
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case 0xdf: rst(); break; |
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@ -282,6 +286,7 @@ void CPU::update() |
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case 0xe6: and8(); break; |
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case 0xe6: and8(); break; |
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case 0xe7: rst(); break; |
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case 0xe7: rst(); break; |
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case 0xe8: adds8(); break; |
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case 0xe8: adds8(); break; |
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case 0xe9: jp16(); break; |
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case 0xea: ldr8(); break; |
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case 0xea: ldr8(); break; |
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case 0xee: xor8(); break; |
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case 0xee: xor8(); break; |
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case 0xef: rst(); break; |
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case 0xef: rst(); break; |
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@ -1361,11 +1366,34 @@ void CPU::call() |
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void CPU::jp16() |
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void CPU::jp16() |
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{ |
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{ |
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auto jump = [this](bool should_jump) -> void { |
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// JP cc,i16
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// Note: the operand is read even when the condition is false
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uint32_t data = pcRead16(); |
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if (!should_jump) { |
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m_wait_cycles += 12; |
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return; |
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} |
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m_wait_cycles += 16; |
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// Jump to address i16 if condition is met; effectively, store i16 into PC
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m_pc = data; |
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}; |
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uint8_t opcode = pcRead(); |
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uint8_t opcode = pcRead(); |
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switch (opcode) { |
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switch (opcode) { |
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case 0xc3: // JP a16
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case 0xc2: /* JP NZ,a16 */ jump(!m_zf); break; |
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m_wait_cycles += 16; |
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case 0xc3: /* JP a16 */ jump(true); break; |
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m_pc = pcRead16(); |
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case 0xca: /* JP Z,a16 */ jump(m_zf); break; |
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case 0xd2: /* JP NC,a16 */ jump(!m_cf); break; |
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case 0xda: /* JP C,a16 */ jump(m_cf); break; |
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case 0xe9: // JP HL
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m_wait_cycles += 4; |
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// Jump to address in HL; effectively, load PC with value in register HL
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m_pc = hl(); |
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break; |
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break; |
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default: |
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default: |
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VERIFY_NOT_REACHED(); |
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VERIFY_NOT_REACHED(); |
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@ -1387,7 +1415,7 @@ void CPU::jrs8() |
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m_wait_cycles += 12; |
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m_wait_cycles += 12; |
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// Relative jump by adding s8 to the address of the instruction following the JR
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// Relative jump by adding s8 to the address of the instruction following the JR
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m_pc = m_pc + signed_data; |
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m_pc = (m_pc + signed_data) & 0xffff; |
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}; |
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}; |
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uint8_t opcode = pcRead(); |
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uint8_t opcode = pcRead(); |
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