Emulator: Implement RLC/RRC opcodes
This commit is contained in:
Riyyi
+92
-2
@@ -14,13 +14,21 @@
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void CPU::prefix()
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{
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// Skip 0xcb opcode
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// Note: All these opcodes are considered 2 bytes, as the prefix is included
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// Skip 0xcb prefix opcode
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m_pc = (m_pc + 1) & 0xffff;
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// Read next opcode
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uint8_t opcode = read(m_pc);
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print("running opcode: {:#04x} @ ({:#06x})\n", opcode, m_pc);
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if (opcode >= 30 && opcode <= 0x3f) {
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if (opcode >= 0x00 && opcode <= 0x07) {
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rlc();
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}
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else if (opcode >= 0x08 && opcode <= 0x0f) {
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rrc();
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}
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else if (opcode >= 0x30 && opcode <= 0x3f) {
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swap();
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}
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else if (opcode >= 0x40 && opcode <= 0x7f) {
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@@ -376,3 +384,85 @@ void CPU::swap()
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VERIFY_NOT_REACHED();
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}
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}
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void CPU::rlc()
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{
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auto rotate_left = [this](uint32_t& register_) -> void {
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// RLC r8, flags: Z 0 0 C
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m_wait_cycles += 8;
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// Copy bit 7 into carry flag
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m_cf = (register_ & 0x80) == 0x80;
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// Rotate register r8 left
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register_ = ((register_ >> 7) | (register_ << 1)) & 0xff;
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// Set other flags
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m_zf = register_ == 0;
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m_nf = 0;
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m_hf = 0;
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};
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uint8_t opcode = pcRead();
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switch (opcode) {
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case 0x00: /* RLC B */ rotate_left(m_b); break;
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case 0x01: /* RLC C */ rotate_left(m_c); break;
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case 0x02: /* RLC D */ rotate_left(m_d); break;
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case 0x03: /* RLC E */ rotate_left(m_e); break;
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case 0x04: /* RLC H */ rotate_left(m_h); break;
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case 0x05: /* RLC L */ rotate_left(m_l); break;
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case 0x06: /* RLC (HL) */ {
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m_wait_cycles += 8; // + 8 = 16 total
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// Rotate the byte pointed to by HL left
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uint32_t data = read(hl());
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rotate_left(data);
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write(hl(), data);
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break;
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}
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case 0x07: /* RLC A */ rotate_left(m_a); break;
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default:
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VERIFY_NOT_REACHED();
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}
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}
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void CPU::rrc()
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{
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auto rotate_right = [this](uint32_t& register_) -> void {
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// RRC r8, flags: Z 0 0 C
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m_wait_cycles += 8;
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// Copy bit 0 into carry flag
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m_cf = (register_ & 0x1) == 0x1;
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// Rotate register r8 right
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register_ = ((register_ >> 1) | (register_ << 7)) & 0xff;
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// Set other flags
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m_zf = register_ == 0;
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m_nf = 0;
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m_hf = 0;
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};
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uint8_t opcode = pcRead();
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switch (opcode) {
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case 0x08: /* RRC B */ rotate_right(m_b); break;
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case 0x09: /* RRC C */ rotate_right(m_c); break;
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case 0x0a: /* RRC D */ rotate_right(m_d); break;
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case 0x0b: /* RRC E */ rotate_right(m_e); break;
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case 0x0c: /* RRC H */ rotate_right(m_h); break;
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case 0x0d: /* RRC L */ rotate_right(m_l); break;
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case 0x0e: /* RRC (HL) */ {
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m_wait_cycles += 8; // + 8 = 16 total
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// Rotate the byte pointed to by HL right
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uint32_t data = read(hl());
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rotate_right(data);
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write(hl(), data);
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break;
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}
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case 0x0f: /* RRC A */ rotate_right(m_a); break;
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default:
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VERIFY_NOT_REACHED();
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}
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}
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+8
-12
@@ -666,8 +666,7 @@ void CPU::ra()
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switch (opcode) {
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case 0x07: // RLCA
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// Rotates A to the left with bit 7 being moved to bit 0 and also stored
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// into the carry
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// Rotates A to the left
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// ┌──────────────┐
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// │ ┌─────────┐ │
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// C <─┴─│7 <── 0│<─┘
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@@ -678,12 +677,11 @@ void CPU::ra()
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m_cf = (m_a & 0x80) == 0x80;
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// Rotate register A left
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m_a = (m_a << 1) | (m_a >> 7);
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m_a = (m_a >> 7) | (m_a << 1);
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break;
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case 0x0f: // RRCA
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// Rotates A to the right with bit 0 being moved to bit 7 and also
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// stored into the carry
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// Rotates A to the right
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// ┌──────────────┐
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// │ ┌─────────┐ │
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// └─>│7 ──> 0│─┴─> C
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@@ -694,12 +692,11 @@ void CPU::ra()
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m_cf = (m_a & 0x1) == 0x1;
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// Rotate register A right
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m_a = (m_a << 7) | (m_a >> 1);
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m_a = (m_a >> 1) | (m_a << 7);
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break;
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case 0x17: { // RLA
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// Rotates A to the left with the carry's value put into bit 0 and bit 7
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// is put into the carry
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// Rotate register A left through carry
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// ┌────────────────────┐
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// │ ┌─────────┐ │
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// └─ C <──│7 <── 0│<─┘
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@@ -710,13 +707,12 @@ void CPU::ra()
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m_cf = (m_a & 0x80) == 0x80; // Copy bit 7 into carry flag
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// Rotate register A left through carry
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m_a = (m_a << 1) | old_carry;
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m_a = old_carry | (m_a << 1);
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break;
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}
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case 0x1f: { // RRA
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// Rotates A to the right with the carry's value put into bit 7 and bit 0
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// is put into the carry
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// Rotate register A right through carry
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// ┌────────────────────┐
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// │ ┌─────────┐ │
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// └─>│7 ──> 0│──> C ─┘
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@@ -727,7 +723,7 @@ void CPU::ra()
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m_cf = (m_a & 0x1) == 0x1; // Copy bit 0 into carry flag
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// Rotate register A right through carry
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m_a = (old_carry << 7) | (m_a >> 1);
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m_a = (m_a >> 1) | (old_carry << 7);
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break;
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}
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default:
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