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Emulator: Put opcode comment on the case label line

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Riyyi
2022-08-24 19:44:16 +02:00
parent 9f12eaa5ff
commit 4220c4fcd2
1 changed files with 36 additions and 73 deletions
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src/cpu.cpp
+36 -73
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@@ -114,8 +114,7 @@ void CPU::add()
uint8_t opcode = pcRead();
uint8_t immediate = pcRead();
switch (opcode) {
case 0xc6:
// ADD A,i8, flags: Z 0 H C
case 0xc6: // ADD A,i8, flags: Z 0 H C
m_wait_cycles += 8;
// Set flags
@@ -138,8 +137,7 @@ void CPU::dec8()
{
uint8_t opcode = pcRead();
switch (opcode) {
case 0x0d: {
// DEC C, flags: Z 1 H -
case 0x0d: { // DEC C, flags: Z 1 H -
m_wait_cycles += 4;
// Set flags
@@ -162,14 +160,12 @@ void CPU::xor8()
{
uint8_t opcode = pcRead();
switch (opcode) {
case 0xa8:
// XOR B, flags: Z 0 0 0
case 0xa8: // XOR B, flags: Z 0 0 0
m_nf = m_hf = m_cf = 0;
m_a ^= m_b;
m_zf = m_a == 0;
break;
case 0xaf:
// XOR A, flags: 1 0 0 0
case 0xaf: // XOR A, flags: 1 0 0 0
// A ^ A will always be 0
m_a = m_nf = m_hf = m_cf = 0;
m_zf = 1;
@@ -183,77 +179,59 @@ void CPU::ldi8()
{
uint8_t opcode = pcRead();
switch (opcode) {
case 0x06:
// LD B,i8
m_wait_cycles += 8;
case 0x06: // LD B,i8
m_b = pcRead();
break;
case 0x0e:
// LD C,i8
m_wait_cycles += 8;
case 0x0e: // LD C,i8
m_c = pcRead();
break;
case 0x16:
// LD D,i8
m_wait_cycles += 8;
case 0x16: // LD D,i8
m_d = pcRead();
break;
case 0x1e:
// LD E,i8
m_wait_cycles += 8;
case 0x1e: // LD E,i8
m_e = pcRead();
break;
case 0x26:
// LD H,i8
m_wait_cycles += 8;
case 0x26: // LD H,i8
m_h = pcRead();
break;
case 0x2e:
// LD L,i8
m_wait_cycles += 8;
case 0x2e: // LD L,i8
m_l = pcRead();
break;
case 0x36:
// LD (HL),i8
m_wait_cycles += 12;
case 0x36: // LD (HL),i8
m_wait_cycles += 4;
write(hl(), pcRead());
break;
case 0x3e:
// LD A,i8
m_wait_cycles += 8;
case 0x3e: // LD A,i8
m_a = pcRead();
break;
default:
VERIFY_NOT_REACHED();
}
m_wait_cycles += 8;
}
void CPU::ldr8()
{
uint8_t opcode = pcRead();
switch (opcode) {
case 0x02:
// LD (BC),A
case 0x02: // LD (BC),A
m_wait_cycles += 8;
write(bc(), m_a);
break;
case 0x0a:
// LD A,(BC)
case 0x0a: // LD A,(BC)
m_wait_cycles += 8;
m_a = read(bc());
break;
case 0x12:
// LD (DE),A
case 0x12: // LD (DE),A
m_wait_cycles += 8;
write(de(), m_a);
break;
case 0x1a:
// LD A,(DE)
case 0x1a: // LD A,(DE)
m_wait_cycles += 8;
m_a = read(de());
break;
case 0x22: {
// LD (HL+),A == LD (HLI),A == LDI (HL),A
case 0x22: { // LD (HL+),A == LD (HLI),A == LDI (HL),A
m_wait_cycles += 8;
// Put A into memory address in HL
@@ -266,8 +244,7 @@ void CPU::ldr8()
m_h = address >> 8;
break;
}
case 0x2a: {
// LD A,(HL+) == LD A,(HLI) == LDI A,(HL)
case 0x2a: { // LD A,(HL+) == LD A,(HLI) == LDI A,(HL)
m_wait_cycles += 8;
// Put value at address in HL into A
@@ -280,8 +257,7 @@ void CPU::ldr8()
m_h = address >> 8;
break;
}
case 0x32: {
// LD (HL-),A == LD (HLD),A == LDD (HL),A
case 0x32: { // LD (HL-),A == LD (HLD),A == LDD (HL),A
m_wait_cycles += 8;
// Put A into memory address in HL
@@ -294,8 +270,7 @@ void CPU::ldr8()
m_h = address >> 8;
break;
}
case 0x3a: {
// LD A,(HL-) == LD A,(HLD) == LDD A,(HL)
case 0x3a: { // LD A,(HL-) == LD A,(HLD) == LDD A,(HL)
m_wait_cycles += 8;
// Put value at address in HL into A
@@ -317,15 +292,13 @@ void CPU::ldffi8()
{
uint8_t opcode = pcRead();
switch (opcode) {
case 0xe0:
// LD ($ff00 + i8),A == LDH (io8),A
case 0xe0: // LD ($ff00 + i8),A == LDH (io8),A
m_wait_cycles += 12;
// Put value in A into address (0xff00 + next byte in memory)
ffWrite(pcRead(), m_a);
break;
case 0xf0:
// LD A,($ff00 + i8) == LDH A,(io8)
case 0xf0: // LD A,($ff00 + i8) == LDH A,(io8)
m_wait_cycles += 12;
// Put value at address (0xff00 + next byte in memory) into A
@@ -340,37 +313,32 @@ void CPU::ld16()
{
uint8_t opcode = pcRead();
switch (opcode) {
case 0x01: {
case 0x01: { // LD BC,i16
m_wait_cycles += 12;
write(bc(), pcRead16());
break;
}
case 0x08: {
// LD a16,SP
case 0x08: { // LD a16,SP
m_wait_cycles += 20;
// Put value of SP into address given by next 2 bytes in memory
// TODO
break;
}
case 0x11:
// LD DE,i16
case 0x11: // LD DE,i16
m_wait_cycles += 12;
write(de(), pcRead16());
break;
case 0x21:
// LD HL,i16
case 0x21: // LD HL,i16
m_wait_cycles += 12;
write(hl(), pcRead16());
break;
case 0x31: {
// LD SP,i16
case 0x31: { // LD SP,i16
m_wait_cycles += 12;
m_sp = pcRead16();
break;
}
case 0xf8: {
// LD HL,SP + s8 == LDHL SP,s8, flags: 0 0 H C
case 0xf8: { // LD HL,SP + s8 == LDHL SP,s8, flags: 0 0 H C
m_wait_cycles += 12;
// Put SP + next (signed) byte in memory into HL
@@ -386,8 +354,7 @@ void CPU::ld16()
m_cf = isCarry(m_sp, signed_data, 0x100);
break;
}
case 0xf9: {
// LD SP,HL
case 0xf9: { // LD SP,HL
m_wait_cycles += 8;
m_sp = hl();
break;
@@ -401,8 +368,7 @@ void CPU::call()
{
uint8_t opcode = pcRead();
switch (opcode) {
case 0xcd: {
// CALL a16
case 0xcd: { // CALL a16
m_wait_cycles += 24;
uint32_t data = pcRead16();
@@ -426,8 +392,7 @@ void CPU::jp16()
{
uint8_t opcode = pcRead();
switch (opcode) {
case 0xc3:
// JP a16
case 0xc3: // JP a16
m_wait_cycles += 16;
m_pc = pcRead16();
break;
@@ -441,8 +406,7 @@ void CPU::jr8()
{
uint8_t opcode = pcRead();
switch (opcode) {
case 0x20: {
// JR NZ,s8
case 0x20: { // JR NZ,s8
m_wait_cycles += 8;
if (!m_zf) {
@@ -460,8 +424,7 @@ void CPU::misc()
{
uint8_t opcode = pcRead();
switch (opcode) {
case 0x2f:
// CPL, flags: - 1 1 -
case 0x2f: // CPL, flags: - 1 1 -
m_wait_cycles += 4;
// Complement register A (flip all bits)