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@ -69,31 +69,39 @@ void CPU::update()
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case 0x01: ldi16(); break; |
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case 0x02: ldr8(); break; |
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case 0x04: inc(); break; |
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case 0x06: ldi8(); break; |
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case 0x08: ldr16(); break; |
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case 0x0a: ldr8(); break; |
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case 0x0b: decr16(); break; |
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case 0x0c: inc(); break; |
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case 0x0d: dec8(); break; |
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case 0x0e: ldi8(); break; |
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case 0x11: ldi16(); break; |
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case 0x12: ldr8(); break; |
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case 0x14: inc(); break; |
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case 0x16: ldi8(); break; |
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case 0x1a: ldr8(); break; |
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case 0x1b: decr16(); break; |
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case 0x1c: inc(); break; |
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case 0x1e: ldi8(); break; |
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case 0x20: jr8(); break; |
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case 0x21: ldi16(); break; |
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case 0x22: ldr8(); break; |
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case 0x24: inc(); break; |
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case 0x26: ldi8(); break; |
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case 0x2a: lda8(); break; |
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case 0x2b: decr16(); break; |
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case 0x2c: inc(); break; |
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case 0x2e: ldi8(); break; |
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case 0x2f: misc(); break; |
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case 0x31: ldi16(); break; |
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case 0x32: ldr8(); break; |
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case 0x34: inc(); break; |
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case 0x36: ldi8(); break; |
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case 0x3a: ldr8(); break; |
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case 0x3b: decr16(); break; |
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case 0x3c: inc(); break; |
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case 0x3e: ldi8(); break; |
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case 0x40: ldr8(); break; |
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case 0x41: ldr8(); break; |
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@ -154,6 +162,14 @@ void CPU::update()
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case 0x7f: ldr8(); break; |
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case 0xa8: xor8(); break; |
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case 0xaf: xor8(); break; |
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case 0xb8: cp(); break; |
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case 0xb9: cp(); break; |
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case 0xba: cp(); break; |
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case 0xbb: cp(); break; |
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case 0xbc: cp(); break; |
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case 0xbd: cp(); break; |
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case 0xbe: cp(); break; |
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case 0xbf: cp(); break; |
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case 0xc3: jp16(); break; |
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case 0xc6: add(); break; |
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case 0xcd: call(); break; |
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@ -165,6 +181,7 @@ void CPU::update()
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case 0xf8: ldr16(); break; |
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case 0xf9: ldr16(); break; |
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case 0xfa: lda8(); break; |
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case 0xfe: cp(); break; |
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default: |
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print("opcode {:#x} not implemented\n", opcode); |
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@ -481,6 +498,93 @@ void CPU::ldr8()
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m_wait_cycles += 4; |
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} |
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void CPU::cp() |
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{ |
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uint8_t opcode = pcRead(); |
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uint8_t value = 0; |
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switch (opcode) { |
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case 0xb8: /* CP B */ value = m_b; break; |
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case 0xb9: /* CP C */ value = m_c; break; |
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case 0xba: /* CP D */ value = m_d; break; |
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case 0xbb: /* CP E */ value = m_e; break; |
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case 0xbc: /* CP H */ value = m_h; break; |
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case 0xbd: /* CP L */ value = m_l; break; |
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case 0xbe: // CP,(HL)
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m_wait_cycles += 4; |
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value = read(hl()); |
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break; |
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case 0xbf: // CP A, flags: 1 1 0 0
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m_wait_cycles += 4; |
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// A - A
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m_zf = m_nf = 1; |
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m_hf = m_cf = 0; |
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return; // Early return as we already set the flags
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case 0xfe: // CP i8
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m_wait_cycles += 4; |
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value = pcRead(); |
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break; |
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default: |
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VERIFY_NOT_REACHED(); |
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} |
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// CP r8, flags: Z 1 H C
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m_wait_cycles += 4; |
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// Set flags
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m_zf = ((m_a - value) & 0xff) == 0; |
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m_nf = 1; |
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m_hf = isCarry(m_a, value, 0x10); |
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m_cf = isCarry(m_a, value, 0x100); |
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} |
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void CPU::inc() |
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{ |
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auto increment = [this](uint32_t& reg) -> void { |
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// INC r8, flags: Z 0 H -
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m_wait_cycles += 4; |
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// Set flags
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m_nf = 0; |
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m_hf = isCarry(reg, 1, 0x10); |
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// Increment value in register r8 by 1
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reg = (reg + 1) & 0xff; |
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// Zero flag
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m_zf = reg == 0; |
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}; |
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uint8_t opcode = pcRead(); |
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switch (opcode) { |
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case 0x04: /* INC B */ increment(m_b); break; |
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case 0x0c: /* INC C */ increment(m_c); break; |
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case 0x14: /* INC D */ increment(m_d); break; |
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case 0x1c: /* INC E */ increment(m_e); break; |
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case 0x24: /* INC H */ increment(m_h); break; |
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case 0x2c: /* INC L */ increment(m_l); break; |
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case 0x34: { /* INC (HL) */ |
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m_wait_cycles += 12; |
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uint32_t data = read(hl()); |
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// Set flags
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m_nf = 0; |
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m_hf = isCarry(data, 1, 0x10); |
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// Increment the byte pointed to by HL by 1
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data = (data + 1) & 0xff; |
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write(hl(), data); |
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// Zero flag
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m_zf = data == 0; |
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break; |
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} |
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case 0x3c: /* INC A */ increment(m_a); break; |
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default: |
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VERIFY_NOT_REACHED(); |
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} |
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} |
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void CPU::ldffi8() |
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{ |
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uint8_t opcode = pcRead(); |
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