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@ -70,7 +70,7 @@ void CPU::update()
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case 0x00: nop(); break; |
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case 0x01: ldi16(); break; |
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case 0x02: ldr8(); break; |
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case 0x04: inc(); break; |
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case 0x04: inc8(); break; |
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case 0x05: dec8(); break; |
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case 0x06: ldi8(); break; |
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case 0x07: ra(); break; |
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@ -78,13 +78,13 @@ void CPU::update()
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case 0x09: addr16(); break; |
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case 0x0a: ldr8(); break; |
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case 0x0b: dec16(); break; |
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case 0x0c: inc(); break; |
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case 0x0c: inc8(); break; |
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case 0x0d: dec8(); break; |
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case 0x0e: ldi8(); break; |
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case 0x0f: ra(); break; |
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case 0x11: ldi16(); break; |
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case 0x12: ldr8(); break; |
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case 0x14: inc(); break; |
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case 0x14: inc8(); break; |
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case 0x15: dec8(); break; |
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case 0x16: ldi8(); break; |
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case 0x17: ra(); break; |
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@ -92,35 +92,35 @@ void CPU::update()
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case 0x19: addr16(); break; |
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case 0x1a: ldr8(); break; |
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case 0x1b: dec16(); break; |
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case 0x1c: inc(); break; |
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case 0x1c: inc8(); break; |
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case 0x1d: dec8(); break; |
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case 0x1e: ldi8(); break; |
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case 0x1f: ra(); break; |
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case 0x20: jrs8(); break; |
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case 0x21: ldi16(); break; |
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case 0x22: ldr8(); break; |
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case 0x24: inc(); break; |
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case 0x24: inc8(); break; |
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case 0x25: dec8(); break; |
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case 0x26: ldi8(); break; |
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case 0x28: jrs8(); break; |
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case 0x29: addr16(); break; |
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case 0x2a: lda8(); break; |
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case 0x2b: dec16(); break; |
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case 0x2c: inc(); break; |
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case 0x2c: inc8(); break; |
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case 0x2d: dec8(); break; |
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case 0x2e: ldi8(); break; |
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case 0x2f: misc(); break; |
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case 0x30: jrs8(); break; |
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case 0x31: ldi16(); break; |
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case 0x32: ldr8(); break; |
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case 0x34: inc(); break; |
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case 0x34: inc8(); break; |
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case 0x35: dec8(); break; |
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case 0x36: ldi8(); break; |
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case 0x38: jrs8(); break; |
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case 0x39: addr16(); break; |
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case 0x3a: ldr8(); break; |
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case 0x3b: dec16(); break; |
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case 0x3c: inc(); break; |
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case 0x3c: inc8(); break; |
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case 0x3d: dec8(); break; |
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case 0x3e: ldi8(); break; |
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case 0x40: ldr8(); break; |
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@ -367,6 +367,46 @@ void CPU::dec8()
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} |
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} |
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void CPU::inc8() |
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{ |
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auto increment = [this](uint32_t& register_) -> void { |
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// INC r8, flags: Z 0 H -
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m_wait_cycles += 4; |
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// Set flags
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m_nf = 0; |
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m_hf = isCarry(register_, 1, 0x10); |
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// Increment value in register r8 by 1
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register_ = (register_ + 1) & 0xff; |
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// Zero flag
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m_zf = register_ == 0; |
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}; |
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uint8_t opcode = pcRead(); |
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switch (opcode) { |
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case 0x04: /* INC B */ increment(m_b); break; |
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case 0x0c: /* INC C */ increment(m_c); break; |
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case 0x14: /* INC D */ increment(m_d); break; |
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case 0x1c: /* INC E */ increment(m_e); break; |
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case 0x24: /* INC H */ increment(m_h); break; |
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case 0x2c: /* INC L */ increment(m_l); break; |
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case 0x34: /* INC (HL) */ { |
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m_wait_cycles += 8; // + 4 = 12 total
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// Increment the byte pointed to by HL by 1
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uint32_t data = read(hl()); |
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increment(data); |
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write(hl(), data); |
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break; |
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} |
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case 0x3c: /* INC A */ increment(m_a); break; |
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default: |
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VERIFY_NOT_REACHED(); |
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} |
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} |
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void CPU::xor8() |
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{ |
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uint8_t opcode = pcRead(); |
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@ -801,46 +841,6 @@ void CPU::cp()
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m_cf = isCarry(m_a, value, 0x100); |
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} |
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void CPU::inc() |
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{ |
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auto increment = [this](uint32_t& register_) -> void { |
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// INC r8, flags: Z 0 H -
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m_wait_cycles += 4; |
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// Set flags
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m_nf = 0; |
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m_hf = isCarry(register_, 1, 0x10); |
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// Increment value in register r8 by 1
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register_ = (register_ + 1) & 0xff; |
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// Zero flag
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m_zf = register_ == 0; |
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}; |
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uint8_t opcode = pcRead(); |
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switch (opcode) { |
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case 0x04: /* INC B */ increment(m_b); break; |
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case 0x0c: /* INC C */ increment(m_c); break; |
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case 0x14: /* INC D */ increment(m_d); break; |
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case 0x1c: /* INC E */ increment(m_e); break; |
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case 0x24: /* INC H */ increment(m_h); break; |
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case 0x2c: /* INC L */ increment(m_l); break; |
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case 0x34: /* INC (HL) */ { |
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m_wait_cycles += 8; // + 4 = 12 total
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// Increment the byte pointed to by HL by 1
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uint32_t data = read(hl()); |
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increment(data); |
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write(hl(), data); |
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break; |
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} |
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case 0x3c: /* INC A */ increment(m_a); break; |
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default: |
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VERIFY_NOT_REACHED(); |
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} |
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} |
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void CPU::ldffi8() |
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{ |
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uint8_t opcode = pcRead(); |
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