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Emulator: Some cleanup in the CPU class

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Riyyi
2022-08-22 21:49:24 +02:00
parent c83d322d0c
commit afedc8a30b
1 changed files with 17 additions and 13 deletions
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src/cpu.cpp
+17 -13
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@@ -58,7 +58,9 @@ void CPU::update()
if (m_wait_cycles <= 0) { if (m_wait_cycles <= 0) {
// Read next opcode // Read next opcode
uint8_t opcode = peekMemory(); uint8_t opcode = peekMemory();
print("running opcode: {:#x}\n", opcode);
switch (opcode) { switch (opcode) {
case 0x01: ld16(); break; case 0x01: ld16(); break;
case 0x08: ld16(); break; case 0x08: ld16(); break;
case 0x11: ld16(); break; case 0x11: ld16(); break;
@@ -71,13 +73,12 @@ void CPU::update()
case 0xf0: ldh8(); break; case 0xf0: ldh8(); break;
case 0xf8: ld16(); break; case 0xf8: ld16(); break;
case 0xf9: ld16(); break; case 0xf9: ld16(); break;
default: default:
print("opcode {:#x} not implemented", opcode); print("opcode {:#x} not implemented\n", opcode);
VERIFY_NOT_REACHED(); VERIFY_NOT_REACHED();
} }
} }
// print("This is an update from the CPU\n");
} }
void CPU::add() void CPU::add()
@@ -99,7 +100,7 @@ void CPU::add()
m_a += immediate; m_a += immediate;
// Drop overflown bits, the 'A' register is 8-bit // Drop overflown bits, the 'A' register is 8-bit
m_a &= 0xff; m_a &= 0x00ff;
break; break;
default: default:
VERIFY_NOT_REACHED(); VERIFY_NOT_REACHED();
@@ -111,8 +112,9 @@ void CPU::ld8()
uint8_t opcode = read(m_pc++); uint8_t opcode = read(m_pc++);
switch (opcode) { switch (opcode) {
case 0x3e: case 0x3e:
// LD A,n
m_wait_cycles += 8; m_wait_cycles += 8;
m_a = immediate8(); m_a = read(m_pc++);
break; break;
default: default:
VERIFY_NOT_REACHED(); VERIFY_NOT_REACHED();
@@ -125,15 +127,17 @@ void CPU::ldh8()
switch (opcode) { switch (opcode) {
case 0xe0: case 0xe0:
// LD ($ff00 + n),A == LDH (n),A // LD ($ff00 + n),A == LDH (n),A
// Put value in A into address (0xff00 + next byte in memory):
m_wait_cycles += 12; m_wait_cycles += 12;
// Put value in A into address (0xff00 + next byte in memory)
writeFf(m_a); writeFf(m_a);
break; break;
case 0xf0: case 0xf0:
// LD A,($ff00 + n) == LDH A,(n) // LD A,($ff00 + n) == LDH A,(n)
// Put value at address (0xff00 + next byte in memory) into A:
m_wait_cycles += 12; m_wait_cycles += 12;
m_a = readFf(immediate8());
// Put value at address (0xff00 + next byte in memory) into A
m_a = readFf(read(m_pc++));
break; break;
default: default:
VERIFY_NOT_REACHED(); VERIFY_NOT_REACHED();
@@ -149,6 +153,11 @@ void CPU::ld16()
write(bc(), immediate16()); write(bc(), immediate16());
break; break;
} }
case 0x08: {
m_wait_cycles += 20;
// TODO
break;
}
case 0x11: case 0x11:
m_wait_cycles += 12; m_wait_cycles += 12;
write(de(), immediate16()); write(de(), immediate16());
@@ -162,11 +171,6 @@ void CPU::ld16()
m_sp = immediate16(); m_sp = immediate16();
break; break;
} }
case 0x08: {
m_wait_cycles += 20;
// TODO
break;
}
case 0xf8: { case 0xf8: {
m_wait_cycles += 12; m_wait_cycles += 12;
// TODO // TODO