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@ -127,8 +127,6 @@ void CPU::update() |
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switch (opcode) { |
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switch (opcode) { |
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case 0x10: /* TODO */ m_pc += 2; break; |
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case 0x10: /* TODO */ m_pc += 2; break; |
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case 0xf3: /* TODO */ m_pc += 1; break; |
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case 0xfb: /* TODO */ m_pc += 1; break; |
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case 0x00: nop(); break; |
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case 0x00: nop(); break; |
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case 0x01: ldi16(); break; |
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case 0x01: ldi16(); break; |
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@ -363,12 +361,14 @@ void CPU::update() |
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case 0xf0: ldff8(); break; |
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case 0xf0: ldff8(); break; |
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case 0xf1: pop(); break; |
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case 0xf1: pop(); break; |
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case 0xf2: ldff8(); break; |
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case 0xf2: ldff8(); break; |
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case 0xf3: misc(); break; |
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case 0xf5: push(); break; |
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case 0xf5: push(); break; |
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case 0xf6: or8(); break; |
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case 0xf6: or8(); break; |
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case 0xf7: rst(); break; |
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case 0xf7: rst(); break; |
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case 0xf8: ldr16(); break; |
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case 0xf8: ldr16(); break; |
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case 0xf9: ldr16(); break; |
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case 0xf9: ldr16(); break; |
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case 0xfa: lda8(); break; |
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case 0xfa: lda8(); break; |
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case 0xfb: misc(); break; |
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case 0xfe: cp(); break; |
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case 0xfe: cp(); break; |
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case 0xff: rst(); break; |
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case 0xff: rst(); break; |
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@ -1601,8 +1601,8 @@ void CPU::ret() |
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case 0xd8: /* RET C,i16 */ function_return(m_cf); break; |
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case 0xd8: /* RET C,i16 */ function_return(m_cf); break; |
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case 0xd9: /* RETI */ { |
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case 0xd9: /* RETI */ { |
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// Return from subroutine
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// Return from subroutine
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// TODO: and enable interrupts.
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function_return(true); |
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function_return(true); |
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m_ime = true; |
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break; |
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break; |
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} |
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} |
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default: |
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default: |
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@ -1669,6 +1669,19 @@ void CPU::misc() |
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// Invert carry
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// Invert carry
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m_cf = (m_cf) ? 0 : 1; |
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m_cf = (m_cf) ? 0 : 1; |
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break; |
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break; |
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case 0xf3: // DI
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m_wait_cycles += 4; |
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// Disable Interrupts by clearing the IME flag
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m_ime = 0; |
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break; |
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case 0xfb: // EI
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m_wait_cycles += 4; |
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// Enable Interrupts by setting the IME flag.
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// The flag is only set after the instruction following EI
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m_should_enable_ime = true; |
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break; |
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default: |
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default: |
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VERIFY_NOT_REACHED(); |
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VERIFY_NOT_REACHED(); |
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} |
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} |
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