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418 lines
7.5 KiB
418 lines
7.5 KiB
/* |
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* Copyright (C) 2022 Riyyi |
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* Copyright (C) 2022 Th3FrankXD |
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* |
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* SPDX-License-Identifier: MIT |
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*/ |
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#include <cstdint> // int32_t, uint8_t, uint32_t |
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#include "cpu.h" |
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#include "emu.h" |
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#include "ruc/format/print.h" |
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#include "ruc/meta/assert.h" |
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CPU::CPU(uint32_t frequency) |
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: ProcessingUnit(frequency) |
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// https://gbdev.io/pandocs/Power_Up_Sequence.html#cpu-registers |
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// CGB registers |
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, m_a(0x11) |
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, m_b(0x0) |
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, m_c(0x0) |
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, m_d(0xff) |
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, m_e(0x56) |
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, m_h(0x0) |
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, m_l(0x0d) |
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, m_pc(0x0) |
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, m_sp(0xfffe) |
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// Flags |
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, m_zf(0x1) |
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, m_nf(0x0) |
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, m_hf(0x0) |
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, m_cf(0x0) |
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{ |
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m_shared_registers.emplace("a", &m_a); |
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m_shared_registers.emplace("b", &m_b); |
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m_shared_registers.emplace("c", &m_c); |
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m_shared_registers.emplace("d", &m_d); |
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m_shared_registers.emplace("e", &m_e); |
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m_shared_registers.emplace("h", &m_h); |
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m_shared_registers.emplace("l", &m_l); |
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m_shared_registers.emplace("sp", &m_sp); |
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m_shared_registers.emplace("pc", &m_pc); |
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m_shared_registers.emplace("zf", &m_zf); |
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m_shared_registers.emplace("nf", &m_nf); |
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m_shared_registers.emplace("hf", &m_hf); |
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m_shared_registers.emplace("cf", &m_cf); |
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} |
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CPU::~CPU() |
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{ |
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} |
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// ----------------------------------------- |
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void CPU::update() |
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{ |
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m_wait_cycles--; |
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if (m_wait_cycles <= 0) { |
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// Read next opcode |
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uint8_t opcode = read(m_pc); |
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print("running opcode: {:#x}\n", opcode); |
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switch (opcode) { |
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case 0x01: ld16(); break; |
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case 0x02: ld8(); break; |
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case 0x06: ld8(); break; |
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case 0x08: ld16(); break; |
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case 0x0a: ld8(); break; |
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case 0x0e: ld8(); break; |
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case 0x11: ld16(); break; |
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case 0x12: ld8(); break; |
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case 0x16: ld8(); break; |
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case 0x1a: ld8(); break; |
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case 0x1e: ld8(); break; |
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case 0x21: ld16(); break; |
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case 0x22: ld8(); break; |
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case 0x26: ld8(); break; |
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case 0x2a: ld8(); break; |
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case 0x2e: ld8(); break; |
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case 0x31: ld16(); break; |
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case 0x32: ld8(); break; |
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case 0x36: ld8(); break; |
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case 0x3a: ld8(); break; |
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case 0x3e: ld8(); break; |
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case 0xa8: xor8(); break; |
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case 0xaf: xor8(); break; |
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case 0xc3: jp16(); break; |
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case 0xc6: add(); break; |
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case 0xcd: call(); break; |
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case 0xe0: ldh8(); break; |
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case 0xf0: ldh8(); break; |
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case 0xf8: ld16(); break; |
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case 0xf9: ld16(); break; |
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default: |
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print("opcode {:#x} not implemented\n", opcode); |
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VERIFY_NOT_REACHED(); |
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} |
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} |
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} |
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void CPU::add() |
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{ |
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uint8_t opcode = pcRead(); |
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uint8_t immediate = pcRead(); |
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switch (opcode) { |
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case 0xc6: |
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// ADD A,d8 |
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m_wait_cycles += 8; |
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// Flags: Z0HC |
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m_zf = m_a + immediate == 0; |
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m_nf = 0; |
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m_hf = m_a + immediate > 16; |
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m_cf = m_a + immediate > 255; |
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// A = A + r |
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m_a += immediate; |
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// Drop overflown bits, the 'A' register is 8-bit |
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m_a &= 0x00ff; |
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break; |
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default: |
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VERIFY_NOT_REACHED(); |
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} |
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} |
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void CPU::xor8() |
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{ |
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uint8_t opcode = pcRead(); |
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switch (opcode) { |
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case 0xa8: |
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// XOR B, flags: Z 0 0 0 |
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m_nf = m_hf = m_cf = 0; |
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m_a ^= m_b; |
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m_zf = m_a == 0; |
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break; |
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case 0xaf: |
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// XOR A, flags: 1 0 0 0 |
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// A^A will always be 0 |
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m_a = m_nf = m_hf = m_cf = 0; |
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m_zf = 1; |
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break; |
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default: |
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VERIFY_NOT_REACHED(); |
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} |
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} |
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void CPU::ld8() |
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{ |
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uint8_t opcode = pcRead(); |
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switch (opcode) { |
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case 0x02: |
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// LD (BC),A |
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m_wait_cycles += 8; |
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write(bc(), m_a); |
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break; |
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case 0x06: |
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// LD B,n |
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m_wait_cycles += 8; |
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m_b = pcRead(); |
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break; |
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case 0x0a: |
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// LD A,(BC) |
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m_wait_cycles += 8; |
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m_a = read(bc()); |
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break; |
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case 0x0e: |
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// LD C,n |
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m_wait_cycles += 8; |
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m_c = pcRead(); |
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break; |
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case 0x12: |
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// LD (DE),A |
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m_wait_cycles += 8; |
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write(de(), m_a); |
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break; |
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case 0x16: |
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// LD D,n |
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m_wait_cycles += 8; |
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m_d = pcRead(); |
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break; |
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case 0x1a: |
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// LD A,(DE) |
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m_wait_cycles += 8; |
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m_a = read(de()); |
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break; |
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case 0x1e: |
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// LD E,n |
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m_wait_cycles += 8; |
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m_e = pcRead(); |
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break; |
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case 0x22: { |
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// LD (HL+),A == LD (HLI),A == LDI (HL),A |
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m_wait_cycles += 8; |
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// Put A into memory address in HL |
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uint32_t address = hl(); |
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write(address, m_a); |
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// Increment HL |
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address = (address + 1) & 0xffff; |
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m_l = address & 0x00ff; |
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m_h = address >> 8; |
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break; |
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} |
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case 0x26: |
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// LD H,n |
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m_wait_cycles += 8; |
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m_h = pcRead(); |
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break; |
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case 0x2a: { |
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// LD A,(HL+) == LD A,(HLI) == LDI A,(HL) |
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m_wait_cycles += 8; |
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// Put value at address in HL into A |
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uint32_t address = hl(); |
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m_a = read(address); |
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// Increment HL |
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address = (address + 1) & 0xffff; |
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m_l = address & 0x00ff; |
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m_h = address >> 8; |
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break; |
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} |
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case 0x2e: |
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// LD L,n |
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m_wait_cycles += 8; |
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m_l = pcRead(); |
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break; |
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case 0x32: { |
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// LD (HL-),A == LD (HLD),A == LDD (HL),A |
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m_wait_cycles += 8; |
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// Put A into memory address in HL |
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uint32_t address = hl(); |
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write(address, m_a); |
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// Decrement HL |
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address = (address - 1) & 0xffff; |
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m_l = address & 0x00ff; |
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m_h = address >> 8; |
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break; |
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} |
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case 0x36: |
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// LD (HL),n |
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m_wait_cycles += 12; |
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write(hl(), pcRead()); |
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break; |
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case 0x3a: { |
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// LD A,(HL-) == LD A,(HLD) == LDD A,(HL) |
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m_wait_cycles += 8; |
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// Put value at address in HL into A |
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uint32_t address = hl(); |
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m_a = read(address); |
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// Decrement HL |
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address = (address + 1) & 0xffff; |
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m_l = address & 0x00ff; |
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m_h = address >> 8; |
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break; |
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} |
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case 0x3e: |
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// LD A,n |
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m_wait_cycles += 8; |
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m_a = pcRead(); |
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break; |
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default: |
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VERIFY_NOT_REACHED(); |
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} |
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} |
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void CPU::ldh8() |
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{ |
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uint8_t opcode = pcRead(); |
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switch (opcode) { |
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case 0xe0: |
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// LD ($ff00 + n),A == LDH (n),A |
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m_wait_cycles += 12; |
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// Put value in A into address (0xff00 + next byte in memory) |
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ffWrite(pcRead(), m_a); |
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break; |
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case 0xf0: |
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// LD A,($ff00 + n) == LDH A,(n) |
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m_wait_cycles += 12; |
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// Put value at address (0xff00 + next byte in memory) into A |
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m_a = ffRead(pcRead()); |
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break; |
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default: |
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VERIFY_NOT_REACHED(); |
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} |
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} |
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void CPU::ld16() |
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{ |
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uint8_t opcode = pcRead(); |
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switch (opcode) { |
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case 0x01: { |
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m_wait_cycles += 12; |
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write(bc(), pcRead16()); |
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break; |
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} |
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case 0x08: { |
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// LD (nn),SP |
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m_wait_cycles += 20; |
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// Put value of SP into address given by next 2 bytes in memory |
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// TODO |
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break; |
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} |
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case 0x11: |
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// LD DE,nn |
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m_wait_cycles += 12; |
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write(de(), pcRead16()); |
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break; |
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case 0x21: |
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// LD HL,nn |
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m_wait_cycles += 12; |
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write(hl(), pcRead16()); |
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break; |
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case 0x31: { |
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// LD SP,nn |
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m_wait_cycles += 12; |
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m_sp = pcRead16(); |
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break; |
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} |
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case 0xf8: { |
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// LD HL,SP + e8 == LDHL SP,e8 |
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m_wait_cycles += 12; |
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// Put SP + next (signed) byte in memory into HL |
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// TODO |
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// Unsets ZF and NF, may enable HF and CF |
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// TODO flags |
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break; |
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} |
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case 0xf9: { |
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// LD SP,HL |
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m_wait_cycles += 8; |
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m_sp = hl(); |
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break; |
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} |
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default: |
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VERIFY_NOT_REACHED(); |
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} |
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} |
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void CPU::call() |
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{ |
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uint8_t opcode = pcRead(); |
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switch (opcode) { |
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case 0xcd: { |
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// CALL nn |
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m_wait_cycles += 24; |
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uint32_t data = pcRead16(); |
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// Push address of next 2 bytes in memory onto stack |
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m_sp = (m_sp - 1) & 0xffff; |
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write(m_sp, data >> 8); |
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m_sp = (m_sp - 1) & 0xffff; |
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write(m_sp, data & 0x00ff); |
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// Jump to this address |
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m_pc = data; |
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break; |
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} |
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default: |
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VERIFY_NOT_REACHED(); |
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} |
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} |
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void CPU::jp16() |
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{ |
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uint8_t opcode = pcRead(); |
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switch (opcode) { |
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case 0xc3: |
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// JP nn |
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m_wait_cycles += 16; |
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m_pc = pcRead16(); |
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break; |
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default: |
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VERIFY_NOT_REACHED(); |
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} |
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} |
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// ----------------------------------------- |
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uint32_t CPU::pcRead() |
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{ |
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uint32_t data = Emu::the().readMemory(m_pc) & 0x00ff; |
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m_pc = (m_pc + 1) & 0xffff; |
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return data; |
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} |
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void CPU::write(uint32_t address, uint32_t value) |
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{ |
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Emu::the().writeMemory(address, value & 0x00ff); |
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} |
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uint32_t CPU::read(uint32_t address) |
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{ |
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return Emu::the().readMemory(address) & 0x00ff; |
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} |
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void CPU::ffWrite(uint32_t address, uint32_t value) |
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{ |
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Emu::the().writeMemory(address | (0xff << 8), value & 0x00ff); |
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} |
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uint32_t CPU::ffRead(uint32_t address) |
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{ |
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return Emu::the().readMemory(address | (0xff << 8)) & 0x00ff; |
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}
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