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@ -120,6 +120,7 @@ void CPU::update() |
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case 0x34: inc8(); break; |
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case 0x34: inc8(); break; |
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case 0x35: dec8(); break; |
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case 0x35: dec8(); break; |
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case 0x36: ldi8(); break; |
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case 0x36: ldi8(); break; |
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case 0x37: misc(); break; |
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case 0x38: jrs8(); break; |
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case 0x38: jrs8(); break; |
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case 0x39: addr16(); break; |
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case 0x39: addr16(); break; |
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case 0x3a: ldr8(); break; |
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case 0x3a: ldr8(); break; |
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@ -127,6 +128,7 @@ void CPU::update() |
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case 0x3c: inc8(); break; |
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case 0x3c: inc8(); break; |
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case 0x3d: dec8(); break; |
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case 0x3d: dec8(); break; |
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case 0x3e: ldi8(); break; |
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case 0x3e: ldi8(); break; |
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case 0x3f: misc(); break; |
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case 0x40: ldr8(); break; |
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case 0x40: ldr8(); break; |
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case 0x41: ldr8(); break; |
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case 0x41: ldr8(); break; |
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case 0x42: ldr8(); break; |
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case 0x42: ldr8(); break; |
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@ -1104,11 +1106,26 @@ void CPU::misc() |
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m_wait_cycles += 4; |
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m_wait_cycles += 4; |
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// Complement register A (flip all bits)
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// Complement register A (flip all bits)
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m_a ^= 0xff; // equivalent to: m_a = ~m_a & 0xff
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m_a = (~m_a) & 0xff; |
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// Set flags
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// Set flags
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m_nf = m_hf = 1; |
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m_nf = m_hf = 1; |
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break; |
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break; |
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case 0x37: // SCF, flags: - 0 0 1
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m_wait_cycles += 4; |
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// Set flags
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m_nf = m_hf = 0; |
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m_cf = 1; |
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break; |
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case 0x3f: // CCF, flags: - 0 0 C
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m_wait_cycles += 4; |
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// Set flags
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m_nf = m_hf = 0; |
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// Invert carry
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m_cf = (m_cf) ? 0 : 1; |
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break; |
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default: |
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default: |
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VERIFY_NOT_REACHED(); |
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VERIFY_NOT_REACHED(); |
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} |
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} |
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