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Emulator: Reorganize 8-bit load opcode functions

master
Riyyi 2 years ago
parent
commit
9f12eaa5ff
  1. 129
      src/cpu.cpp
  2. 5
      src/cpu.h

129
src/cpu.cpp

@ -69,35 +69,35 @@ void CPU::update()
case 0x20: jr8(); break; case 0x20: jr8(); break;
case 0x01: ld16(); break; case 0x01: ld16(); break;
case 0x02: ld8(); break; case 0x02: ldr8(); break;
case 0x06: ld8(); break; case 0x06: ldi8(); break;
case 0x08: ld16(); break; case 0x08: ld16(); break;
case 0x0a: ld8(); break; case 0x0a: ldr8(); break;
case 0x0d: dec8(); break; case 0x0d: dec8(); break;
case 0x0e: ld8(); break; case 0x0e: ldi8(); break;
case 0x11: ld16(); break; case 0x11: ld16(); break;
case 0x12: ld8(); break; case 0x12: ldr8(); break;
case 0x16: ld8(); break; case 0x16: ldi8(); break;
case 0x1a: ld8(); break; case 0x1a: ldr8(); break;
case 0x1e: ld8(); break; case 0x1e: ldi8(); break;
case 0x21: ld16(); break; case 0x21: ld16(); break;
case 0x22: ld8(); break; case 0x22: ldr8(); break;
case 0x26: ld8(); break; case 0x26: ldi8(); break;
case 0x2a: ld8(); break; case 0x2a: ldr8(); break;
case 0x2e: ld8(); break; case 0x2e: ldi8(); break;
case 0x2f: misc(); break; case 0x2f: misc(); break;
case 0x31: ld16(); break; case 0x31: ld16(); break;
case 0x32: ld8(); break; case 0x32: ldr8(); break;
case 0x36: ld8(); break; case 0x36: ldi8(); break;
case 0x3a: ld8(); break; case 0x3a: ldr8(); break;
case 0x3e: ld8(); break; case 0x3e: ldi8(); break;
case 0xa8: xor8(); break; case 0xa8: xor8(); break;
case 0xaf: xor8(); break; case 0xaf: xor8(); break;
case 0xc3: jp16(); break; case 0xc3: jp16(); break;
case 0xc6: add(); break; case 0xc6: add(); break;
case 0xcd: call(); break; case 0xcd: call(); break;
case 0xe0: ldh8(); break; case 0xe0: ldffi8(); break;
case 0xf0: ldh8(); break; case 0xf0: ldffi8(); break;
case 0xf8: ld16(); break; case 0xf8: ld16(); break;
case 0xf9: ld16(); break; case 0xf9: ld16(); break;
@ -179,50 +179,79 @@ void CPU::xor8()
} }
} }
void CPU::ld8() void CPU::ldi8()
{ {
uint8_t opcode = pcRead(); uint8_t opcode = pcRead();
switch (opcode) { switch (opcode) {
case 0x02:
// LD (BC),A
m_wait_cycles += 8;
write(bc(), m_a);
break;
case 0x06: case 0x06:
// LD B,i8 // LD B,i8
m_wait_cycles += 8; m_wait_cycles += 8;
m_b = pcRead(); m_b = pcRead();
break; break;
case 0x0a:
// LD A,(BC)
m_wait_cycles += 8;
m_a = read(bc());
break;
case 0x0e: case 0x0e:
// LD C,i8 // LD C,i8
m_wait_cycles += 8; m_wait_cycles += 8;
m_c = pcRead(); m_c = pcRead();
break; break;
case 0x12:
// LD (DE),A
m_wait_cycles += 8;
write(de(), m_a);
break;
case 0x16: case 0x16:
// LD D,i8 // LD D,i8
m_wait_cycles += 8; m_wait_cycles += 8;
m_d = pcRead(); m_d = pcRead();
break; break;
case 0x1a:
// LD A,(DE)
m_wait_cycles += 8;
m_a = read(de());
break;
case 0x1e: case 0x1e:
// LD E,i8 // LD E,i8
m_wait_cycles += 8; m_wait_cycles += 8;
m_e = pcRead(); m_e = pcRead();
break; break;
case 0x26:
// LD H,i8
m_wait_cycles += 8;
m_h = pcRead();
break;
case 0x2e:
// LD L,i8
m_wait_cycles += 8;
m_l = pcRead();
break;
case 0x36:
// LD (HL),i8
m_wait_cycles += 12;
write(hl(), pcRead());
break;
case 0x3e:
// LD A,i8
m_wait_cycles += 8;
m_a = pcRead();
break;
default:
VERIFY_NOT_REACHED();
}
}
void CPU::ldr8()
{
uint8_t opcode = pcRead();
switch (opcode) {
case 0x02:
// LD (BC),A
m_wait_cycles += 8;
write(bc(), m_a);
break;
case 0x0a:
// LD A,(BC)
m_wait_cycles += 8;
m_a = read(bc());
break;
case 0x12:
// LD (DE),A
m_wait_cycles += 8;
write(de(), m_a);
break;
case 0x1a:
// LD A,(DE)
m_wait_cycles += 8;
m_a = read(de());
break;
case 0x22: { case 0x22: {
// LD (HL+),A == LD (HLI),A == LDI (HL),A // LD (HL+),A == LD (HLI),A == LDI (HL),A
m_wait_cycles += 8; m_wait_cycles += 8;
@ -237,11 +266,6 @@ void CPU::ld8()
m_h = address >> 8; m_h = address >> 8;
break; break;
} }
case 0x26:
// LD H,i8
m_wait_cycles += 8;
m_h = pcRead();
break;
case 0x2a: { case 0x2a: {
// LD A,(HL+) == LD A,(HLI) == LDI A,(HL) // LD A,(HL+) == LD A,(HLI) == LDI A,(HL)
m_wait_cycles += 8; m_wait_cycles += 8;
@ -256,11 +280,6 @@ void CPU::ld8()
m_h = address >> 8; m_h = address >> 8;
break; break;
} }
case 0x2e:
// LD L,i8
m_wait_cycles += 8;
m_l = pcRead();
break;
case 0x32: { case 0x32: {
// LD (HL-),A == LD (HLD),A == LDD (HL),A // LD (HL-),A == LD (HLD),A == LDD (HL),A
m_wait_cycles += 8; m_wait_cycles += 8;
@ -275,11 +294,6 @@ void CPU::ld8()
m_h = address >> 8; m_h = address >> 8;
break; break;
} }
case 0x36:
// LD (HL),i8
m_wait_cycles += 12;
write(hl(), pcRead());
break;
case 0x3a: { case 0x3a: {
// LD A,(HL-) == LD A,(HLD) == LDD A,(HL) // LD A,(HL-) == LD A,(HLD) == LDD A,(HL)
m_wait_cycles += 8; m_wait_cycles += 8;
@ -294,17 +308,12 @@ void CPU::ld8()
m_h = address >> 8; m_h = address >> 8;
break; break;
} }
case 0x3e:
// LD A,i8
m_wait_cycles += 8;
m_a = pcRead();
break;
default: default:
VERIFY_NOT_REACHED(); VERIFY_NOT_REACHED();
} }
} }
void CPU::ldh8() void CPU::ldffi8()
{ {
uint8_t opcode = pcRead(); uint8_t opcode = pcRead();
switch (opcode) { switch (opcode) {

5
src/cpu.h

@ -44,8 +44,9 @@ public:
// Load Instructions // Load Instructions
// 8-bit // 8-bit
void ld8(); void ldffi8();
void ldh8(); void ldi8();
void ldr8();
// 16-bit // 16-bit
void ld16(); void ld16();

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