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@ -69,35 +69,35 @@ void CPU::update() |
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case 0x20: jr8(); break; |
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case 0x20: jr8(); break; |
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case 0x01: ld16(); break; |
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case 0x01: ld16(); break; |
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case 0x02: ld8(); break; |
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case 0x02: ldr8(); break; |
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case 0x06: ld8(); break; |
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case 0x06: ldi8(); break; |
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case 0x08: ld16(); break; |
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case 0x08: ld16(); break; |
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case 0x0a: ld8(); break; |
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case 0x0a: ldr8(); break; |
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case 0x0d: dec8(); break; |
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case 0x0d: dec8(); break; |
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case 0x0e: ld8(); break; |
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case 0x0e: ldi8(); break; |
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case 0x11: ld16(); break; |
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case 0x11: ld16(); break; |
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case 0x12: ld8(); break; |
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case 0x12: ldr8(); break; |
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case 0x16: ld8(); break; |
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case 0x16: ldi8(); break; |
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case 0x1a: ld8(); break; |
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case 0x1a: ldr8(); break; |
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case 0x1e: ld8(); break; |
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case 0x1e: ldi8(); break; |
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case 0x21: ld16(); break; |
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case 0x21: ld16(); break; |
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case 0x22: ld8(); break; |
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case 0x22: ldr8(); break; |
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case 0x26: ld8(); break; |
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case 0x26: ldi8(); break; |
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case 0x2a: ld8(); break; |
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case 0x2a: ldr8(); break; |
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case 0x2e: ld8(); break; |
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case 0x2e: ldi8(); break; |
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case 0x2f: misc(); break; |
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case 0x2f: misc(); break; |
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case 0x31: ld16(); break; |
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case 0x31: ld16(); break; |
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case 0x32: ld8(); break; |
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case 0x32: ldr8(); break; |
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case 0x36: ld8(); break; |
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case 0x36: ldi8(); break; |
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case 0x3a: ld8(); break; |
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case 0x3a: ldr8(); break; |
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case 0x3e: ld8(); break; |
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case 0x3e: ldi8(); break; |
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case 0xa8: xor8(); break; |
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case 0xa8: xor8(); break; |
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case 0xaf: xor8(); break; |
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case 0xaf: xor8(); break; |
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case 0xc3: jp16(); break; |
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case 0xc3: jp16(); break; |
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case 0xc6: add(); break; |
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case 0xc6: add(); break; |
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case 0xcd: call(); break; |
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case 0xcd: call(); break; |
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case 0xe0: ldh8(); break; |
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case 0xe0: ldffi8(); break; |
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case 0xf0: ldh8(); break; |
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case 0xf0: ldffi8(); break; |
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case 0xf8: ld16(); break; |
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case 0xf8: ld16(); break; |
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case 0xf9: ld16(); break; |
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case 0xf9: ld16(); break; |
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@ -179,50 +179,79 @@ void CPU::xor8() |
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} |
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} |
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} |
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} |
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void CPU::ld8() |
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void CPU::ldi8() |
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{ |
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{ |
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uint8_t opcode = pcRead(); |
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uint8_t opcode = pcRead(); |
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switch (opcode) { |
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switch (opcode) { |
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case 0x02: |
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// LD (BC),A
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m_wait_cycles += 8; |
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write(bc(), m_a); |
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break; |
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case 0x06: |
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case 0x06: |
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// LD B,i8
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// LD B,i8
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m_wait_cycles += 8; |
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m_wait_cycles += 8; |
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m_b = pcRead(); |
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m_b = pcRead(); |
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break; |
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break; |
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case 0x0a: |
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// LD A,(BC)
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m_wait_cycles += 8; |
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m_a = read(bc()); |
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break; |
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case 0x0e: |
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case 0x0e: |
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// LD C,i8
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// LD C,i8
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m_wait_cycles += 8; |
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m_wait_cycles += 8; |
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m_c = pcRead(); |
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m_c = pcRead(); |
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break; |
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break; |
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case 0x12: |
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// LD (DE),A
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m_wait_cycles += 8; |
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write(de(), m_a); |
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break; |
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case 0x16: |
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case 0x16: |
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// LD D,i8
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// LD D,i8
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m_wait_cycles += 8; |
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m_wait_cycles += 8; |
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m_d = pcRead(); |
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m_d = pcRead(); |
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break; |
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break; |
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case 0x1a: |
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// LD A,(DE)
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m_wait_cycles += 8; |
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m_a = read(de()); |
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break; |
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case 0x1e: |
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case 0x1e: |
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// LD E,i8
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// LD E,i8
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m_wait_cycles += 8; |
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m_wait_cycles += 8; |
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m_e = pcRead(); |
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m_e = pcRead(); |
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break; |
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break; |
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case 0x26: |
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// LD H,i8
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m_wait_cycles += 8; |
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m_h = pcRead(); |
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break; |
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case 0x2e: |
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// LD L,i8
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m_wait_cycles += 8; |
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m_l = pcRead(); |
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break; |
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case 0x36: |
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// LD (HL),i8
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m_wait_cycles += 12; |
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write(hl(), pcRead()); |
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break; |
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case 0x3e: |
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// LD A,i8
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m_wait_cycles += 8; |
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m_a = pcRead(); |
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break; |
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default: |
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VERIFY_NOT_REACHED(); |
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} |
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} |
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void CPU::ldr8() |
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{ |
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uint8_t opcode = pcRead(); |
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switch (opcode) { |
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case 0x02: |
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// LD (BC),A
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m_wait_cycles += 8; |
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write(bc(), m_a); |
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break; |
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case 0x0a: |
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// LD A,(BC)
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m_wait_cycles += 8; |
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m_a = read(bc()); |
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break; |
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case 0x12: |
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// LD (DE),A
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m_wait_cycles += 8; |
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write(de(), m_a); |
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break; |
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case 0x1a: |
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// LD A,(DE)
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m_wait_cycles += 8; |
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m_a = read(de()); |
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break; |
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case 0x22: { |
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case 0x22: { |
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// LD (HL+),A == LD (HLI),A == LDI (HL),A
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// LD (HL+),A == LD (HLI),A == LDI (HL),A
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m_wait_cycles += 8; |
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m_wait_cycles += 8; |
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@ -237,11 +266,6 @@ void CPU::ld8() |
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m_h = address >> 8; |
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m_h = address >> 8; |
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break; |
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break; |
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} |
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} |
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case 0x26: |
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// LD H,i8
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m_wait_cycles += 8; |
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m_h = pcRead(); |
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break; |
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case 0x2a: { |
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case 0x2a: { |
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// LD A,(HL+) == LD A,(HLI) == LDI A,(HL)
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// LD A,(HL+) == LD A,(HLI) == LDI A,(HL)
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m_wait_cycles += 8; |
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m_wait_cycles += 8; |
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@ -256,11 +280,6 @@ void CPU::ld8() |
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m_h = address >> 8; |
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m_h = address >> 8; |
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break; |
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break; |
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} |
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} |
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case 0x2e: |
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// LD L,i8
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m_wait_cycles += 8; |
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m_l = pcRead(); |
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break; |
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case 0x32: { |
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case 0x32: { |
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// LD (HL-),A == LD (HLD),A == LDD (HL),A
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// LD (HL-),A == LD (HLD),A == LDD (HL),A
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m_wait_cycles += 8; |
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m_wait_cycles += 8; |
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@ -275,11 +294,6 @@ void CPU::ld8() |
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m_h = address >> 8; |
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m_h = address >> 8; |
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break; |
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break; |
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} |
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} |
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case 0x36: |
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// LD (HL),i8
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m_wait_cycles += 12; |
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write(hl(), pcRead()); |
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break; |
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case 0x3a: { |
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case 0x3a: { |
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// LD A,(HL-) == LD A,(HLD) == LDD A,(HL)
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// LD A,(HL-) == LD A,(HLD) == LDD A,(HL)
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m_wait_cycles += 8; |
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m_wait_cycles += 8; |
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@ -294,17 +308,12 @@ void CPU::ld8() |
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m_h = address >> 8; |
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m_h = address >> 8; |
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break; |
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break; |
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} |
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} |
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case 0x3e: |
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// LD A,i8
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m_wait_cycles += 8; |
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m_a = pcRead(); |
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break; |
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default: |
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default: |
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VERIFY_NOT_REACHED(); |
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VERIFY_NOT_REACHED(); |
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} |
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} |
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} |
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} |
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void CPU::ldh8() |
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void CPU::ldffi8() |
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{ |
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{ |
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uint8_t opcode = pcRead(); |
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uint8_t opcode = pcRead(); |
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switch (opcode) { |
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switch (opcode) { |
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