Emulator: Separate pixel FIFO states into different functions

Most of these were broken on the carry and half-carry calculation.

.gitmodules

@@ -1,3 +1,3 @@
-[submodule "vendor/ruc"]
-	path = vendor/ruc
-	url = https://github.com/riyyi/ruc
+[submodule "vendor/inferno"]
+	path = vendor/inferno
+	url = https://github.com/riyyi/inferno

CMakeLists.txt

@@ -52,21 +52,28 @@ set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
 # ------------------------------------------
 # Library
 
-set(RUC_BUILD_TESTS OFF)
-add_subdirectory("vendor/ruc")
+set(INFERNO_BUILD_EXAMPLES OFF)
+add_subdirectory("vendor/inferno")
 
 # ------------------------------------------
 # Application target
 
 # Define source files
 file(GLOB_RECURSE PROJECT_SOURCES "src/*.cpp")
-set(PROJECT_SOURCES ${PROJECT_SOURCES})
 
 add_executable(${PROJECT} ${PROJECT_SOURCES})
 target_include_directories(${PROJECT} PRIVATE
-	"src"
-	"vendor/ruc/src")
-target_link_libraries(${PROJECT} ruc)
+	"src")
+target_link_libraries(${PROJECT} inferno)
+
+# ------------------------------------------
+# Assets target
+
+add_custom_target(${PROJECT}-assets
+	COMMAND ${CMAKE_COMMAND} -P ${CMAKE_CURRENT_SOURCE_DIR}/cmake/copy-assets.cmake
+	WORKING_DIRECTORY ${CMAKE_BINARY_DIR})
+add_dependencies(${PROJECT} ${PROJECT}-assets)
+add_dependencies(${PROJECT}-assets inferno-assets) # Copy project assets *AFTER* engine assets!
 
 # ------------------------------------------
 # Execute target
@@ -87,9 +94,6 @@ if (GARBAGE_BUILD_TESTS)
 	add_executable(${PROJECT}-unit-test ${TEST_SOURCES})
 	target_include_directories(${PROJECT}-unit-test PRIVATE
 		"src"
-		"test"
-		"vendor/ruc/src"
-		"vendor/ruc/test")
-	target_link_libraries(${PROJECT}-unit-test ruc)
-	target_link_libraries(${PROJECT}-unit-test ruc-test)
+		"test")
+	target_link_libraries(${PROJECT}-unit-test inferno)
 endif()

README.org

@@ -10,14 +10,13 @@ Accurate GameBoy emulator.
 *** Clone
 
 #+BEGIN_SRC shell-script
-$ git clone https://gitlab.com/riyyi/garbage
+$ git clone https://github.com/riyyi/garbage
 $ cd garbage
-$ git submodule init
-$ git submodule update
+$ git submodule update --init --recursive
 #+END_SRC
 Or
 #+BEGIN_SRC shell-script
-$ git clone --recursive https://gitlab.com/riyyi/garbage
+$ git clone --recursive https://github.com/riyyi/garbage
 #+END_SRC
 
 *** Update

assets/scene/scene1.json

@@ -0,0 +1,16 @@
+{
+	"camera": {
+		"name": "Camera",
+		"translate": [ 0.0, 0.0, -1.0 ],
+		"rotate": [ 0.0, 0.0, 0.0 ],
+		"scale": [ 1.0, 1.0, 1.0 ],
+		"type": "orthographic",
+		"zoom-level": 0.45
+	},
+	"quad" : [
+		{
+			"name": "Screen",
+			"scale": [ 1.0, -0.9, 1.0 ]
+		}
+	]
+}

assets/settings.json

@@ -0,0 +1,9 @@
+{
+	"window": {
+		"fullscreen": "windowed",
+		"height": 432,
+		"title": "GarbAGE",
+		"vsync": true,
+		"width": 480
+	}
+}

cmake/copy-assets.cmake

@@ -0,0 +1 @@
+file(COPY ${CMAKE_CURRENT_LIST_DIR}/../assets DESTINATION ${CMAKE_CURRENT_BINARY_DIR})

doc/terminology.org

@@ -7,42 +7,79 @@ GameBoy terminology.
 
 ** Terminology
 
-*** Hardware
+*** Hardware [[#references][(1)]][[#references][(2)]]
 
 | Name            | Modern equivalent | Description                               |
 |-----------------+-------------------+-------------------------------------------|
-| APU             |                   | Audio Processing Unit                     |
+| APU             | Sound card        | Audio Processing Unit                     |
 | PPU             | GPU               | Pixel Processing Unit                     |
 | Bootrom         | BIOS              |                                           |
 | HRAM (High RAM) | CPU cache         | Embedded memory inside the CPU, 127 bytes |
 | WRAM (Work RAM) | RAM               |                                           |
 
+*** Flags
+
+The half-carry flag ~H~ is set when an arithmetic operation on two numbers
+causes a carry from bit #3 to bit #4 for 8-bit operations or a carry from bit
+#11 to bit #12 for 16-bit operations. For 16-bit operation this indicates the
+lower 4 bits of the *second* byte[[#references][(3)]].
+
+We start counting from the right as bit *#0*!
+
 *** Opcode
 
 | Name      | Bits | Sign     | Mnemonics |    [[https://gbdev.io/gb-opcodes/optables/][1]] |   [[https://rgbds.gbdev.io/docs/v0.5.2/gbz80.7/][2]] |  [[https://gekkio.fi/files/gb-docs/gbctr.pdf][3]]/[[http://marc.rawer.de/Gameboy/Docs/GBCPUman.pdf][3]] |   [[https://gbdev.io/pandocs/CPU_Instruction_Set.html][4]] | Description                  | Note                   |
-|-----------+------+----------+-----------+------+-----+------+-----+------------------------------+-------------------|
+|-----------+------+----------+-----------+------+-----+------+-----+------------------------------+------------------------|
 |           |      |          |           |  <r> | <r> |  <r> | <r> |                              |                        |
-| immediate |    8 | unsigned |           |   d8 |  n8 |    n |     | Next byte in memory          |                   |
-| immediate |   16 | unsigned |           |  d16 | n16 |   nn |     | Next byte in memory          | little-endian     |
-| register  |    8 | unsigned |           |      |  r8 |    r |     | Any of the registers         |                   |
-| register  |   16 | unsigned |           |      | r16 |   rr |     | Any of the registers         | little-endian     |
-| address   |    8 | unsigned |           |      |     |  (n) |     | Address at value             |                   |
-| address   |   16 | unsigned |           |  a16 | n16 | (nn) |  nn | Address at value             | little-endian     |
-| immediate |    8 | signed   |           |   r8 |  e8 |    e |  dd | Next byte in memory          |                   |
-| immediate |    8 | unsigned |           | (a8) | n16 |  (n) |   n | 0xff00 + next byte in memory | write to I/O-port |
-| condition |      |          |           |   NZ |  cc |      |   f | Execute if condition met     |                   |
+| immediate |    8 | unsigned | i8        |   d8 |  n8 |    n |     | Next byte in memory          |                        |
+| immediate |   16 | unsigned | i16       |  d16 | n16 |   nn |     | Next byte in memory          | little-endian          |
+| register  |    8 | unsigned | r8        |      |  r8 |    r |     | Any of the registers         |                        |
+| register  |   16 | unsigned | r16       |      | r16 |   rr |     | Any of the registers         | little-endian          |
+| address   |    8 | unsigned | a8        |      |     |  (n) |     | Address at value             |                        |
+| address   |   16 | unsigned | a16 or () |  a16 | n16 | (nn) |  nn | Address at value             | little-endian          |
+| immediate |    8 | signed   | s8        |   r8 |  e8 |    e |  dd | Next byte in memory          | used as offset         |
+| immediate |    8 | unsigned | io8       | (a8) | n16 |  (n) |   n | 0xff00 + next byte in memory | write to I/O-port      |
+| condition |      |          | <ZNHC>    |      |  cc |      |   f | Execute if condition met     |                        |
+| constant  |    8 | unsigned | b         |      |  u3 |    b |   n | Single bit at position 'x'   |                        |
+| constant  |    8 | unsigned | vec       |      | vec |      |   n | One of RST vectors           | absolute fixed address |
 
 d = data \\
 n = constant
 
+**** Flag conditions
+
+Flag conditions, sometimes referred to as ~cc~, are the state the flags need to
+be in to execute the opcode. There are four possible checks[[#references][(4)]][[#references][(5)]]:
+
+| Code | Meaning                        | State |
+|------+--------------------------------+-------|
+| Z    | Execute if Zero flag is set    |     1 |
+| NZ   | Execute if Zero flag is unset  |     0 |
+| C    | Execute if Carry flag is set   |     1 |
+| NC   | Execute if Carry flag is unset |     0 |
+
+**** RST vectors
+
+Absolute fixed address, possible values are[[#references][(4)]]: ~0x00~, ~0x08~, ~0x10~, ~0x18~,
+~0x20~, ~0x28~, ~0x30~, and ~0x38~.
+
 *** Variables
 
 | Name   | Meaning                |
-|--------+--------------------|
+|--------+------------------------|
 | length | amount of elements     |
 | size   | amount of bytes        |
+|--------+------------------------|
+| lhs    | left hand side         |
+| rhs    | right hand side        |
+|--------+------------------------|
+| lsb    | least significant byte |
+| msb    | most significant byte  |
 
 ** References
 
-- https://gbdev.io/pandocs/Memory_Map.html
-- https://gbdev.io/pandocs/Specifications.html
+1. [[https://gbdev.io/pandocs/Memory_Map.html]["Memory Map"]]. rgbdev.io. Retrieved 22 Aug 2022.
+2. [[https://gbdev.io/pandocs/Specifications.html]["Specifications"]]. rgbdev.io. Retrieved 22 Aug 2022.
+3. [[https://robdor.com/2016/08/10/gameboy-emulator-half-carry-flag/]["A Visual Guide to the Gameboy's Half-Carry Flag"]]. robdor.com. Retrieved 24 Aug 2022.
+4. [[https://rgbds.gbdev.io/docs/v0.5.2/gbz80.7#LEGEND]["gbz80(7) — CPU opcode reference"]]. rgbds.gbdev.io. Retrieved 26 Aug 2022.
+5. [[http://www.devrs.com/gb/files/opcodes.html]["GameBoy Opcode Summary"]]. devrs.com. Retrieved 25 Aug 2022.

script/opcode-check.sh

@@ -0,0 +1,23 @@
+#!/bin/sh
+
+# Get the full path to this script while handling spaces and symlinks correctly
+scriptPath="$(cd -P -- "$(dirname -- "$0")" && pwd -P)"
+cd "$scriptPath/.." || exit 1
+
+opcode_check() {
+	path="$1"
+	file="$(basename "$path")"
+
+	max=255
+	for i in $(seq 1 "$max")
+	do
+		opcode=$(printf "0x%.2x\n" "$i")
+		# Pattern: case 0x??:
+		if ! grep -q "case $opcode:" "$path"; then
+			echo "missing opcode: $opcode in $file"
+		fi
+	done
+}
+
+opcode_check "src/cpu.cpp"
+opcode_check "src/cpu-prefix.cpp"

src/cpu-prefix.cpp

@@ -0,0 +1,704 @@
+/*
+ * Copyright (C) 2022 Riyyi
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#include <cstdint> // uint8_t, uint32_t
+
+#include "cpu.h"
+#include "ruc/format/print.h"
+#include "ruc/meta/assert.h"
+
+void CPU::prefix()
+{
+	// Note: All these opcodes are considered 2 bytes, as the prefix is included
+
+	// Skip 0xcb prefix opcode
+	m_pc = (m_pc + 1) & 0xffff;
+
+	// Read next opcode
+	uint8_t opcode = read(m_pc);
+	// print("running opcode: {:#04x} @ ({:#06x})\n", opcode, m_pc);
+	if (opcode <= 0x07) {
+		rlc();
+	}
+	else if (opcode >= 0x08 && opcode <= 0x0f) {
+		rrc();
+	}
+	else if (opcode >= 0x10 && opcode <= 0x17) {
+		rl();
+	}
+	else if (opcode >= 0x18 && opcode <= 0x1f) {
+		rr();
+	}
+	else if (opcode >= 0x20 && opcode <= 0x27) {
+		sla();
+	}
+	else if (opcode >= 0x28 && opcode <= 0x2f) {
+		sra();
+	}
+	else if (opcode >= 0x30 && opcode <= 0x37) {
+		swap();
+	}
+	else if (opcode >= 0x38 && opcode <= 0x3f) {
+		srl();
+	}
+	else if (opcode >= 0x40 && opcode <= 0x7f) {
+		bit();
+	}
+	else if (opcode >= 0x80 && opcode <= 0xbf) {
+		res();
+	}
+	else if (opcode >= 0xc0) {
+		set();
+	}
+	else {
+		print("opcode {:#04x} not implemented\n", opcode);
+		print("immediate: {:#04x}\n", pcRead());
+		VERIFY_NOT_REACHED();
+	}
+}
+
+void CPU::bit()
+{
+	auto test_bit = [this](uint32_t bit, uint32_t byte) -> void {
+		// BIT b,r8, flags: Z 0 1 -
+		m_wait_cycles += 8;
+
+		// Set flags
+		// Set zero flag if bit at position 'x' of register r8 is 0
+		m_zf = (byte & bit) == 0x0;
+		m_nf = 0;
+		m_hf = 1;
+	};
+
+	auto test_bit_hl = [this](uint32_t bit) -> void {
+		// BIT b,(HL), flags: Z 0 1 -
+		m_wait_cycles += 12;
+
+		// Set flags
+		// Set zero flag if bit at position 'x' of byte pointed by HL is 0
+		m_zf = (read(hl()) & bit) == 0x0;
+		m_nf = 0;
+		m_hf = 1;
+	};
+
+	uint8_t opcode = pcRead();
+	switch (opcode) {
+	case 0x40: /* BIT 0,B */ test_bit(0x01, m_b); break;
+	case 0x41: /* BIT 0,C */ test_bit(0x01, m_c); break;
+	case 0x42: /* BIT 0,D */ test_bit(0x01, m_d); break;
+	case 0x43: /* BIT 0,E */ test_bit(0x01, m_e); break;
+	case 0x44: /* BIT 0,H */ test_bit(0x01, m_h); break;
+	case 0x45: /* BIT 0,L */ test_bit(0x01, m_l); break;
+	case 0x46: /* BIT 0,(HL) */ test_bit_hl(0x01); break;
+	case 0x47: /* BIT 0,A */ test_bit(0x01, m_a); break;
+
+	case 0x48: /* BIT 1,B */ test_bit(0x02, m_b); break;
+	case 0x49: /* BIT 1,C */ test_bit(0x02, m_c); break;
+	case 0x4a: /* BIT 1,D */ test_bit(0x02, m_d); break;
+	case 0x4b: /* BIT 1,E */ test_bit(0x02, m_e); break;
+	case 0x4c: /* BIT 1,H */ test_bit(0x02, m_h); break;
+	case 0x4d: /* BIT 1,L */ test_bit(0x02, m_l); break;
+	case 0x4e: /* BIT 1,(HL) */ test_bit_hl(0x02); break;
+	case 0x4f: /* BIT 1,A */ test_bit(0x02, m_a); break;
+
+	case 0x50: /* BIT 2,B */ test_bit(0x04, m_b); break;
+	case 0x51: /* BIT 2,C */ test_bit(0x04, m_c); break;
+	case 0x52: /* BIT 2,D */ test_bit(0x04, m_d); break;
+	case 0x53: /* BIT 2,E */ test_bit(0x04, m_e); break;
+	case 0x54: /* BIT 2,H */ test_bit(0x04, m_h); break;
+	case 0x55: /* BIT 2,L */ test_bit(0x04, m_l); break;
+	case 0x56: /* BIT 2,(HL) */ test_bit_hl(0x04); break;
+	case 0x57: /* BIT 2,A */ test_bit(0x04, m_a); break;
+
+	case 0x58: /* BIT 3,B */ test_bit(0x08, m_b); break;
+	case 0x59: /* BIT 3,C */ test_bit(0x08, m_c); break;
+	case 0x5a: /* BIT 3,D */ test_bit(0x08, m_d); break;
+	case 0x5b: /* BIT 3,E */ test_bit(0x08, m_e); break;
+	case 0x5c: /* BIT 3,H */ test_bit(0x08, m_h); break;
+	case 0x5d: /* BIT 3,L */ test_bit(0x08, m_l); break;
+	case 0x5e: /* BIT 3,(HL) */ test_bit_hl(0x08); break;
+	case 0x5f: /* BIT 3,A */ test_bit(0x08, m_a); break;
+
+	case 0x60: /* BIT 4,B */ test_bit(0x10, m_b); break;
+	case 0x61: /* BIT 4,C */ test_bit(0x10, m_c); break;
+	case 0x62: /* BIT 4,D */ test_bit(0x10, m_d); break;
+	case 0x63: /* BIT 4,E */ test_bit(0x10, m_e); break;
+	case 0x64: /* BIT 4,H */ test_bit(0x10, m_h); break;
+	case 0x65: /* BIT 4,L */ test_bit(0x10, m_l); break;
+	case 0x66: /* BIT 4,(HL) */ test_bit_hl(0x10); break;
+	case 0x67: /* BIT 4,A */ test_bit(0x10, m_a); break;
+
+	case 0x68: /* BIT 5,B */ test_bit(0x20, m_b); break;
+	case 0x69: /* BIT 5,C */ test_bit(0x20, m_c); break;
+	case 0x6a: /* BIT 5,D */ test_bit(0x20, m_d); break;
+	case 0x6b: /* BIT 5,E */ test_bit(0x20, m_e); break;
+	case 0x6c: /* BIT 5,H */ test_bit(0x20, m_h); break;
+	case 0x6d: /* BIT 5,L */ test_bit(0x20, m_l); break;
+	case 0x6e: /* BIT 5,(HL) */ test_bit_hl(0x20); break;
+	case 0x6f: /* BIT 5,A */ test_bit(0x20, m_a); break;
+
+	case 0x70: /* BIT 6,B */ test_bit(0x40, m_b); break;
+	case 0x71: /* BIT 6,C */ test_bit(0x40, m_c); break;
+	case 0x72: /* BIT 6,D */ test_bit(0x40, m_d); break;
+	case 0x73: /* BIT 6,E */ test_bit(0x40, m_e); break;
+	case 0x74: /* BIT 6,H */ test_bit(0x40, m_h); break;
+	case 0x75: /* BIT 6,L */ test_bit(0x40, m_l); break;
+	case 0x76: /* BIT 6,(HL) */ test_bit_hl(0x40); break;
+	case 0x77: /* BIT 6,A */ test_bit(0x40, m_a); break;
+
+	case 0x78: /* BIT 7,B */ test_bit(0x80, m_b); break;
+	case 0x79: /* BIT 7,C */ test_bit(0x80, m_c); break;
+	case 0x7a: /* BIT 7,D */ test_bit(0x80, m_d); break;
+	case 0x7b: /* BIT 7,E */ test_bit(0x80, m_e); break;
+	case 0x7c: /* BIT 7,H */ test_bit(0x80, m_h); break;
+	case 0x7d: /* BIT 7,L */ test_bit(0x80, m_l); break;
+	case 0x7e: /* BIT 7,(HL) */ test_bit_hl(0x80); break;
+	case 0x7f: /* BIT 7,A */ test_bit(0x80, m_a); break;
+	default:
+		VERIFY_NOT_REACHED();
+	}
+}
+
+void CPU::res()
+{
+	auto reset_bit = [this](uint32_t bit, uint32_t& register_) -> void {
+		// RES b,r8
+		m_wait_cycles += 8;
+
+		// Reset bit at position 'x' in register r8
+		register_ = register_ & (~bit);
+	};
+
+	auto reset_bit_hl = [this](uint32_t bit) -> void {
+		// RES b,(HL)
+		m_wait_cycles += 16;
+
+		// Set bit at postition 'x' in the byte pointed by HL to 0
+		uint32_t data = read(hl());
+		data = data & (~bit);
+		write(hl(), data);
+	};
+
+	uint8_t opcode = pcRead();
+	switch (opcode) {
+	case 0x80: /* RES 0,B */ reset_bit(0x01, m_b); break;
+	case 0x81: /* RES 0,C */ reset_bit(0x01, m_c); break;
+	case 0x82: /* RES 0,D */ reset_bit(0x01, m_d); break;
+	case 0x83: /* RES 0,E */ reset_bit(0x01, m_e); break;
+	case 0x84: /* RES 0,H */ reset_bit(0x01, m_h); break;
+	case 0x85: /* RES 0,L */ reset_bit(0x01, m_l); break;
+	case 0x86: /* RES 0,(HL) */ reset_bit_hl(0x01); break;
+	case 0x87: /* RES 0,A */ reset_bit(0x01, m_a); break;
+
+	case 0x88: /* RES 1,B */ reset_bit(0x02, m_b); break;
+	case 0x89: /* RES 1,C */ reset_bit(0x02, m_c); break;
+	case 0x8a: /* RES 1,D */ reset_bit(0x02, m_d); break;
+	case 0x8b: /* RES 1,E */ reset_bit(0x02, m_e); break;
+	case 0x8c: /* RES 1,H */ reset_bit(0x02, m_h); break;
+	case 0x8d: /* RES 1,L */ reset_bit(0x02, m_l); break;
+	case 0x8e: /* RES 1,(HL) */ reset_bit_hl(0x02); break;
+	case 0x8f: /* RES 1,A */ reset_bit(0x02, m_a); break;
+
+	case 0x90: /* RES 2,B */ reset_bit(0x04, m_b); break;
+	case 0x91: /* RES 2,C */ reset_bit(0x04, m_c); break;
+	case 0x92: /* RES 2,D */ reset_bit(0x04, m_d); break;
+	case 0x93: /* RES 2,E */ reset_bit(0x04, m_e); break;
+	case 0x94: /* RES 2,H */ reset_bit(0x04, m_h); break;
+	case 0x95: /* RES 2,L */ reset_bit(0x04, m_l); break;
+	case 0x96: /* RES 2,(HL) */ reset_bit_hl(0x04); break;
+	case 0x97: /* RES 2,A */ reset_bit(0x04, m_a); break;
+
+	case 0x98: /* RES 3,B */ reset_bit(0x08, m_b); break;
+	case 0x99: /* RES 3,C */ reset_bit(0x08, m_c); break;
+	case 0x9a: /* RES 3,D */ reset_bit(0x08, m_d); break;
+	case 0x9b: /* RES 3,E */ reset_bit(0x08, m_e); break;
+	case 0x9c: /* RES 3,H */ reset_bit(0x08, m_h); break;
+	case 0x9d: /* RES 3,L */ reset_bit(0x08, m_l); break;
+	case 0x9e: /* RES 3,(HL) */ reset_bit_hl(0x08); break;
+	case 0x9f: /* RES 3,A */ reset_bit(0x08, m_a); break;
+
+	case 0xa0: /* RES 4,B */ reset_bit(0x10, m_b); break;
+	case 0xa1: /* RES 4,C */ reset_bit(0x10, m_c); break;
+	case 0xa2: /* RES 4,D */ reset_bit(0x10, m_d); break;
+	case 0xa3: /* RES 4,E */ reset_bit(0x10, m_e); break;
+	case 0xa4: /* RES 4,H */ reset_bit(0x10, m_h); break;
+	case 0xa5: /* RES 4,L */ reset_bit(0x10, m_l); break;
+	case 0xa6: /* RES 4,(HL) */ reset_bit_hl(0x10); break;
+	case 0xa7: /* RES 4,A */ reset_bit(0x10, m_a); break;
+
+	case 0xa8: /* RES 5,B */ reset_bit(0x20, m_b); break;
+	case 0xa9: /* RES 5,C */ reset_bit(0x20, m_c); break;
+	case 0xaa: /* RES 5,D */ reset_bit(0x20, m_d); break;
+	case 0xab: /* RES 5,E */ reset_bit(0x20, m_e); break;
+	case 0xac: /* RES 5,H */ reset_bit(0x20, m_h); break;
+	case 0xad: /* RES 5,L */ reset_bit(0x20, m_l); break;
+	case 0xae: /* RES 5,(HL) */ reset_bit_hl(0x20); break;
+	case 0xaf: /* RES 5,A */ reset_bit(0x20, m_a); break;
+
+	case 0xb0: /* RES 6,B */ reset_bit(0x40, m_b); break;
+	case 0xb1: /* RES 6,C */ reset_bit(0x40, m_c); break;
+	case 0xb2: /* RES 6,D */ reset_bit(0x40, m_d); break;
+	case 0xb3: /* RES 6,E */ reset_bit(0x40, m_e); break;
+	case 0xb4: /* RES 6,H */ reset_bit(0x40, m_h); break;
+	case 0xb5: /* RES 6,L */ reset_bit(0x40, m_l); break;
+	case 0xb6: /* RES 6,(HL) */ reset_bit_hl(0x40); break;
+	case 0xb7: /* RES 6,A */ reset_bit(0x40, m_a); break;
+
+	case 0xb8: /* RES 7,B */ reset_bit(0x80, m_b); break;
+	case 0xb9: /* RES 7,C */ reset_bit(0x80, m_c); break;
+	case 0xba: /* RES 7,D */ reset_bit(0x80, m_d); break;
+	case 0xbb: /* RES 7,E */ reset_bit(0x80, m_e); break;
+	case 0xbc: /* RES 7,H */ reset_bit(0x80, m_h); break;
+	case 0xbd: /* RES 7,L */ reset_bit(0x80, m_l); break;
+	case 0xbe: /* RES 7,(HL) */ reset_bit_hl(0x80); break;
+	case 0xbf: /* RES 7,A */ reset_bit(0x80, m_a); break;
+	default:
+		VERIFY_NOT_REACHED();
+	}
+}
+
+void CPU::set()
+{
+	auto set_bit = [this](uint32_t bit, uint32_t& register_) -> void {
+		// RES b,r8
+		m_wait_cycles += 8;
+
+		// Set bit at position 'x' in register r8
+		register_ = register_ | bit;
+	};
+
+	auto set_bit_hl = [this](uint32_t bit) -> void {
+		// RES b,(HL)
+		m_wait_cycles += 16;
+
+		// Set bit at postition 'x' in the byte pointed by HL to 0
+		uint32_t data = read(hl());
+		data = data | bit;
+		write(hl(), data);
+	};
+
+	uint8_t opcode = pcRead();
+	switch (opcode) {
+	case 0xc0: /* SET 0,B */ set_bit(0x01, m_b); break;
+	case 0xc1: /* SET 0,C */ set_bit(0x01, m_c); break;
+	case 0xc2: /* SET 0,D */ set_bit(0x01, m_d); break;
+	case 0xc3: /* SET 0,E */ set_bit(0x01, m_e); break;
+	case 0xc4: /* SET 0,H */ set_bit(0x01, m_h); break;
+	case 0xc5: /* SET 0,L */ set_bit(0x01, m_l); break;
+	case 0xc6: /* SET 0,(HL) */ set_bit_hl(0x01); break;
+	case 0xc7: /* SET 0,A */ set_bit(0x01, m_a); break;
+
+	case 0xc8: /* SET 1,B */ set_bit(0x02, m_b); break;
+	case 0xc9: /* SET 1,C */ set_bit(0x02, m_c); break;
+	case 0xca: /* SET 1,D */ set_bit(0x02, m_d); break;
+	case 0xcb: /* SET 1,E */ set_bit(0x02, m_e); break;
+	case 0xcc: /* SET 1,H */ set_bit(0x02, m_h); break;
+	case 0xcd: /* SET 1,L */ set_bit(0x02, m_l); break;
+	case 0xce: /* SET 1,(HL) */ set_bit_hl(0x02); break;
+	case 0xcf: /* SET 1,A */ set_bit(0x02, m_a); break;
+
+	case 0xd0: /* SET 2,B */ set_bit(0x04, m_b); break;
+	case 0xd1: /* SET 2,C */ set_bit(0x04, m_c); break;
+	case 0xd2: /* SET 2,D */ set_bit(0x04, m_d); break;
+	case 0xd3: /* SET 2,E */ set_bit(0x04, m_e); break;
+	case 0xd4: /* SET 2,H */ set_bit(0x04, m_h); break;
+	case 0xd5: /* SET 2,L */ set_bit(0x04, m_l); break;
+	case 0xd6: /* SET 2,(HL) */ set_bit_hl(0x04); break;
+	case 0xd7: /* SET 2,A */ set_bit(0x04, m_a); break;
+
+	case 0xd8: /* SET 3,B */ set_bit(0x08, m_b); break;
+	case 0xd9: /* SET 3,C */ set_bit(0x08, m_c); break;
+	case 0xda: /* SET 3,D */ set_bit(0x08, m_d); break;
+	case 0xdb: /* SET 3,E */ set_bit(0x08, m_e); break;
+	case 0xdc: /* SET 3,H */ set_bit(0x08, m_h); break;
+	case 0xdd: /* SET 3,L */ set_bit(0x08, m_l); break;
+	case 0xde: /* SET 3,(HL) */ set_bit_hl(0x08); break;
+	case 0xdf: /* SET 3,A */ set_bit(0x08, m_a); break;
+
+	case 0xe0: /* SET 4,B */ set_bit(0x10, m_b); break;
+	case 0xe1: /* SET 4,C */ set_bit(0x10, m_c); break;
+	case 0xe2: /* SET 4,D */ set_bit(0x10, m_d); break;
+	case 0xe3: /* SET 4,E */ set_bit(0x10, m_e); break;
+	case 0xe4: /* SET 4,H */ set_bit(0x10, m_h); break;
+	case 0xe5: /* SET 4,L */ set_bit(0x10, m_l); break;
+	case 0xe6: /* SET 4,(HL) */ set_bit_hl(0x10); break;
+	case 0xe7: /* SET 4,A */ set_bit(0x10, m_a); break;
+
+	case 0xe8: /* SET 5,B */ set_bit(0x20, m_b); break;
+	case 0xe9: /* SET 5,C */ set_bit(0x20, m_c); break;
+	case 0xea: /* SET 5,D */ set_bit(0x20, m_d); break;
+	case 0xeb: /* SET 5,E */ set_bit(0x20, m_e); break;
+	case 0xec: /* SET 5,H */ set_bit(0x20, m_h); break;
+	case 0xed: /* SET 5,L */ set_bit(0x20, m_l); break;
+	case 0xee: /* SET 5,(HL) */ set_bit_hl(0x20); break;
+	case 0xef: /* SET 5,A */ set_bit(0x20, m_a); break;
+
+	case 0xf0: /* SET 6,B */ set_bit(0x40, m_b); break;
+	case 0xf1: /* SET 6,C */ set_bit(0x40, m_c); break;
+	case 0xf2: /* SET 6,D */ set_bit(0x40, m_d); break;
+	case 0xf3: /* SET 6,E */ set_bit(0x40, m_e); break;
+	case 0xf4: /* SET 6,H */ set_bit(0x40, m_h); break;
+	case 0xf5: /* SET 6,L */ set_bit(0x40, m_l); break;
+	case 0xf6: /* SET 6,(HL) */ set_bit_hl(0x40); break;
+	case 0xf7: /* SET 6,A */ set_bit(0x40, m_a); break;
+
+	case 0xf8: /* SET 7,B */ set_bit(0x80, m_b); break;
+	case 0xf9: /* SET 7,C */ set_bit(0x80, m_c); break;
+	case 0xfa: /* SET 7,D */ set_bit(0x80, m_d); break;
+	case 0xfb: /* SET 7,E */ set_bit(0x80, m_e); break;
+	case 0xfc: /* SET 7,H */ set_bit(0x80, m_h); break;
+	case 0xfd: /* SET 7,L */ set_bit(0x80, m_l); break;
+	case 0xfe: /* SET 7,(HL) */ set_bit_hl(0x80); break;
+	case 0xff: /* SET 7,A */ set_bit(0x80, m_a); break;
+	default:
+		VERIFY_NOT_REACHED();
+	}
+}
+
+void CPU::swap()
+{
+	auto swap_bits = [this](uint32_t& register_) -> void {
+		// SWAP r8, flags: Z 0 0 0
+		m_wait_cycles += 8;
+
+		// Swap upper 4 bits in register r8 with lower 4 bits
+		register_ = ((register_ >> 4) | (register_ << 4)) & 0xff;
+
+		// Set flags
+		m_zf = (register_ == 0);
+		m_nf = 0;
+		m_hf = 0;
+		m_cf = 0;
+	};
+
+	uint8_t opcode = pcRead();
+	switch (opcode) {
+	case 0x30: /* SWAP B */ swap_bits(m_b); break;
+	case 0x31: /* SWAP C */ swap_bits(m_c); break;
+	case 0x32: /* SWAP D */ swap_bits(m_d); break;
+	case 0x33: /* SWAP E */ swap_bits(m_e); break;
+	case 0x34: /* SWAP H */ swap_bits(m_h); break;
+	case 0x35: /* SWAP L */ swap_bits(m_l); break;
+	case 0x36: /* SWAP (HL) */ {
+		m_wait_cycles += 8; // + 8 = 16 total
+
+		// Swap upper 4 bits in the byte pointed by HL with lower 4 bits
+		uint32_t data = read(hl());
+		swap_bits(data);
+		write(hl(), data);
+		break;
+	}
+	case 0x37: /* SWAP A */ swap_bits(m_a); break;
+	default:
+		VERIFY_NOT_REACHED();
+	}
+}
+
+void CPU::rl()
+{
+	auto rotate_left_carry = [this](uint32_t& register_) -> void {
+		// RL r8, flags: Z 0 0 C
+		m_wait_cycles += 8;
+
+		// Copy bit 7 into carry flag
+		uint32_t old_carry = m_cf != 0;
+		m_cf = (register_ & 0x80) == 0x80;
+
+		// Rotate register r8 left through carry
+		register_ = (old_carry | (register_ << 1)) & 0xff;
+
+		// Set other flags
+		m_zf = (register_ == 0);
+		m_nf = 0;
+		m_hf = 0;
+	};
+
+	uint8_t opcode = pcRead();
+	switch (opcode) {
+	case 0x10: /* RL B */ rotate_left_carry(m_b); break;
+	case 0x11: /* RL C */ rotate_left_carry(m_c); break;
+	case 0x12: /* RL D */ rotate_left_carry(m_d); break;
+	case 0x13: /* RL E */ rotate_left_carry(m_e); break;
+	case 0x14: /* RL H */ rotate_left_carry(m_h); break;
+	case 0x15: /* RL L */ rotate_left_carry(m_l); break;
+	case 0x16: /* RL (HL) */ {
+		m_wait_cycles += 8; // + 8 = 16 total
+
+		uint32_t data = read(hl());
+		rotate_left_carry(data);
+		write(hl(), data);
+		break;
+	}
+	case 0x17: /* RL A */ rotate_left_carry(m_a); break;
+	default:
+		VERIFY_NOT_REACHED();
+	}
+}
+
+void CPU::rlc()
+{
+	auto rotate_left = [this](uint32_t& register_) -> void {
+		// RLC r8, flags: Z 0 0 C
+		m_wait_cycles += 8;
+
+		// Copy bit 7 into carry flag
+		m_cf = (register_ & 0x80) == 0x80;
+
+		// Rotate register r8 left
+		register_ = ((register_ >> 7) | (register_ << 1)) & 0xff;
+
+		// Set other flags
+		m_zf = (register_ == 0);
+		m_nf = 0;
+		m_hf = 0;
+	};
+
+	uint8_t opcode = pcRead();
+	switch (opcode) {
+	case 0x00: /* RLC B */ rotate_left(m_b); break;
+	case 0x01: /* RLC C */ rotate_left(m_c); break;
+	case 0x02: /* RLC D */ rotate_left(m_d); break;
+	case 0x03: /* RLC E */ rotate_left(m_e); break;
+	case 0x04: /* RLC H */ rotate_left(m_h); break;
+	case 0x05: /* RLC L */ rotate_left(m_l); break;
+	case 0x06: /* RLC (HL) */ {
+		m_wait_cycles += 8; // + 8 = 16 total
+
+		// Rotate the byte pointed to by HL left
+		uint32_t data = read(hl());
+		rotate_left(data);
+		write(hl(), data);
+		break;
+	}
+	case 0x07: /* RLC A */ rotate_left(m_a); break;
+	default:
+		VERIFY_NOT_REACHED();
+	}
+}
+
+void CPU::rr()
+{
+	auto rotate_right_carry = [this](uint32_t& register_) -> void {
+		// RR r8, flags: Z 0 0 C
+		m_wait_cycles += 8;
+
+		// Copy bit 0 into carry flag
+		uint32_t old_carry = m_cf != 0;
+		m_cf = (register_ & 0x1) == 0x1;
+
+		// Rotate register r8 right through carry
+		register_ = ((register_ >> 1) | (old_carry << 7)) & 0xff;
+
+		// Set other flags
+		m_zf = (register_ == 0);
+		m_nf = 0;
+		m_hf = 0;
+	};
+
+	uint8_t opcode = pcRead();
+	switch (opcode) {
+	case 0x18: /* RR B */ rotate_right_carry(m_b); break;
+	case 0x19: /* RR C */ rotate_right_carry(m_c); break;
+	case 0x1a: /* RR D */ rotate_right_carry(m_d); break;
+	case 0x1b: /* RR E */ rotate_right_carry(m_e); break;
+	case 0x1c: /* RR H */ rotate_right_carry(m_h); break;
+	case 0x1d: /* RR L */ rotate_right_carry(m_l); break;
+	case 0x1e: /* RR (HL) */ {
+		m_wait_cycles += 8; // + 8 = 16 total
+
+		uint32_t data = read(hl());
+		rotate_right_carry(data);
+		write(hl(), data);
+		break;
+	}
+	case 0x1f: /* RR A */ rotate_right_carry(m_a); break;
+	default:
+		VERIFY_NOT_REACHED();
+	}
+}
+
+void CPU::rrc()
+{
+	auto rotate_right = [this](uint32_t& register_) -> void {
+		// RRC r8, flags: Z 0 0 C
+		m_wait_cycles += 8;
+
+		// Copy bit 0 into carry flag
+		m_cf = (register_ & 0x1) == 0x1;
+
+		// Rotate register r8 right
+		register_ = ((register_ >> 1) | (register_ << 7)) & 0xff;
+
+		// Set other flags
+		m_zf = (register_ == 0);
+		m_nf = 0;
+		m_hf = 0;
+	};
+
+	uint8_t opcode = pcRead();
+	switch (opcode) {
+	case 0x08: /* RRC B */ rotate_right(m_b); break;
+	case 0x09: /* RRC C */ rotate_right(m_c); break;
+	case 0x0a: /* RRC D */ rotate_right(m_d); break;
+	case 0x0b: /* RRC E */ rotate_right(m_e); break;
+	case 0x0c: /* RRC H */ rotate_right(m_h); break;
+	case 0x0d: /* RRC L */ rotate_right(m_l); break;
+	case 0x0e: /* RRC (HL) */ {
+		m_wait_cycles += 8; // + 8 = 16 total
+
+		// Rotate the byte pointed to by HL right
+		uint32_t data = read(hl());
+		rotate_right(data);
+		write(hl(), data);
+		break;
+	}
+	case 0x0f: /* RRC A */ rotate_right(m_a); break;
+	default:
+		VERIFY_NOT_REACHED();
+	}
+}
+
+void CPU::sla()
+{
+	auto shift_left_arithmatically = [this](uint32_t& register_) -> void {
+		// SLA r8, flags: Z 0 0 C
+		m_wait_cycles += 8;
+
+		// Shift Left Arithmetically register r8
+		//     ┌─────────┐
+		// C <─│7  <──  0│<─ 0
+		//     └─────────┘
+		//         r8
+
+		// Copy bit 7 into carry flag
+		m_cf = (register_ & 0x80) == 0x80;
+
+		// Shift Left Arithmetically register r8
+		register_ = (register_ << 1) & 0xff;
+
+		// Set other flags
+		m_zf = (register_ == 0);
+		m_nf = 0;
+		m_hf = 0;
+	};
+
+	uint8_t opcode = pcRead();
+	switch (opcode) {
+	case 0x20: /* SLA B */ shift_left_arithmatically(m_b); break;
+	case 0x21: /* SLA C */ shift_left_arithmatically(m_c); break;
+	case 0x22: /* SLA D */ shift_left_arithmatically(m_d); break;
+	case 0x23: /* SLA E */ shift_left_arithmatically(m_e); break;
+	case 0x24: /* SLA H */ shift_left_arithmatically(m_h); break;
+	case 0x25: /* SLA L */ shift_left_arithmatically(m_l); break;
+	case 0x26: /* SLA (HL) */ {
+		m_wait_cycles += 8; // + 8 = 16 total
+
+		// Rotate the byte pointed to by HL right
+		uint32_t data = read(hl());
+		shift_left_arithmatically(data);
+		write(hl(), data);
+		break;
+	}
+	case 0x27: /* SLA A */ shift_left_arithmatically(m_a); break;
+	default:
+		VERIFY_NOT_REACHED();
+	}
+}
+
+void CPU::sra()
+{
+	auto shift_right_arithmatically = [this](uint32_t& register_) -> void {
+		// SRL r8, flags: Z 0 0 C
+		m_wait_cycles += 8;
+
+		// Shift Right Arithmatically register r8
+		//    ┌─────────┐
+		//  ┌─│7  ──>  0│─> C
+		//  │ └─────────┘
+		//  │  ^  r8
+		//  └──┘
+
+		// Copy bit 0 into carry flag
+		m_cf = (register_ & 0x1) == 0x1;
+
+		// Shift Right Arithmatically register r8
+		register_ = (register_ >> 1) | (register_ & 0x80); // Note: bit 7 remains
+
+		// Set other flags
+		m_zf = (register_ == 0);
+		m_nf = 0;
+		m_hf = 0;
+	};
+
+	uint8_t opcode = pcRead();
+	switch (opcode) {
+	case 0x28: /* SRA B */ shift_right_arithmatically(m_b); break;
+	case 0x29: /* SRA C */ shift_right_arithmatically(m_c); break;
+	case 0x2a: /* SRA D */ shift_right_arithmatically(m_d); break;
+	case 0x2b: /* SRA E */ shift_right_arithmatically(m_e); break;
+	case 0x2c: /* SRA H */ shift_right_arithmatically(m_h); break;
+	case 0x2d: /* SRA L */ shift_right_arithmatically(m_l); break;
+	case 0x2e: /* SRA (HL) */ {
+		m_wait_cycles += 8; // + 8 = 16 total
+
+		// Rotate the byte pointed to by HL right
+		uint32_t data = read(hl());
+		shift_right_arithmatically(data);
+		write(hl(), data);
+		break;
+	}
+	case 0x2f: /* SRA A */ shift_right_arithmatically(m_a); break;
+	default:
+		VERIFY_NOT_REACHED();
+	}
+}
+
+void CPU::srl()
+{
+	auto shift_right_logically = [this](uint32_t& register_) -> void {
+		// SRL r8, flags: Z 0 0 C
+		m_wait_cycles += 8;
+
+		// Shift Right Locically register r8
+		//     ┌─────────┐
+		// 0 ─>│7  ──>  0│─> C
+		//     └─────────┘
+		//         r8
+
+		// Copy bit 0 into carry flag
+		m_cf = (register_ & 0x1) == 0x1;
+
+		// Shift Right Locically register r8
+		register_ = (register_ >> 1) & 0x7f; // Note: bit 7 is set to 0
+
+		// Set other flags
+		m_zf = (register_ == 0);
+		m_nf = 0;
+		m_hf = 0;
+	};
+
+	uint8_t opcode = pcRead();
+	switch (opcode) {
+	case 0x38: /* SRL B */ shift_right_logically(m_b); break;
+	case 0x39: /* SRL C */ shift_right_logically(m_c); break;
+	case 0x3a: /* SRL D */ shift_right_logically(m_d); break;
+	case 0x3b: /* SRL E */ shift_right_logically(m_e); break;
+	case 0x3c: /* SRL H */ shift_right_logically(m_h); break;
+	case 0x3d: /* SRL L */ shift_right_logically(m_l); break;
+	case 0x3e: /* SRL (HL) */ {
+		m_wait_cycles += 8; // + 8 = 16 total
+
+		// Shift right logically the byte pointed to by HL
+		uint32_t data = read(hl());
+		shift_right_logically(data);
+		write(hl(), data);
+		break;
+	}
+	case 0x3f: /* SRL A */ shift_right_logically(m_a); break;
+	default:
+		VERIFY_NOT_REACHED();
+	}
+}

src/cpu.h

@@ -7,49 +7,89 @@
 
 #pragma once
 
-#include <cstdint>    // int8_t, int32_t, uint8_t, uint32_t
+#include <cstdint>    // int8_t, uint8_t, uint32_t
 #include <functional> // std::function
 #include <unordered_map>
 
 #include "processing-unit.h"
+#include "ruc/format/formatter.h"
 
 class CPU final : public ProcessingUnit {
+private:
+	friend struct CPUTest;
+
 public:
 	explicit CPU(uint32_t frequency);
 	virtual ~CPU();
 
+	void handleInterrupt(uint32_t interrupt_flag, uint8_t interrupt_source, uint8_t address);
 	void update() override;
 
 	// -------------------------------------
 	// Arithmetic and Logic Instructions
 
 	// 8-bit
-	void add();
+	void adc8();
+	void add8();
+	void and8();
+	void cp();
+	void daa();
+	void dec8();
+	void inc8();
+	void or8();
+	void sbc8();
+	void sub8();
 	void xor8();
 
 	// 16-bit
+	void addr16();
+	void adds8();
+	void dec16();
+	void inc16();
 
 	// -------------------------------------
 	// Bit Operations Instructions
 
+	void bit();
+	void res();
+	void set();
+	void swap();
+
 	// -------------------------------------
 	// Bit Shift Instructions
 
+	void ra();
+	void rl();
+	void rlc();
+	void rr();
+	void rrc();
+	void sla();
+	void sra();
+	void srl();
+
 	// -------------------------------------
 	// Load Instructions
 
 	// 8-bit
-	void ld8();
-	void ldh8();
+	void lda8();
+	void ldff8();
+	void ldi8();
+	void ldr8();
 
 	// 16-bit
-	void ld16();
+	void ldi16();
+	void ldr16();
+	void pop();
+	void push();
 
 	// -------------------------------------
 	// Jumps and Subroutines
 
 	void call();
 	void jp16();
+	void jrs8();
+	void ret();
+	void rst();
 
 	// -------------------------------------
 	// Stack Operations Instructions
@@ -57,6 +97,32 @@ public:
 	// -------------------------------------
 	// Miscellaneous Instructions
 
+	void misc();
+	void nop();
+	void prefix();
+
+	// -------------------------------------
+
+	uint32_t a() const { return m_a; }
+	uint32_t b() const { return m_b; }
+	uint32_t c() const { return m_c; }
+
+	uint32_t af() const { return (m_cf << 4 | m_hf << 5 | m_nf << 6 | m_zf << 7) | m_a << 8; }
+	uint32_t bc() const { return m_c | m_b << 8; }
+	uint32_t de() const { return m_e | m_d << 8; }
+	uint32_t hl() const { return m_l | m_h << 8; }
+	uint32_t pc() const { return m_pc; }
+	uint32_t sp() const { return m_sp; }
+
+	uint32_t zf() const { return m_zf; }
+	uint32_t nf() const { return m_nf; }
+	uint32_t hf() const { return m_hf; }
+	uint32_t cf() const { return m_cf; }
+
+	void setBC(uint32_t value);
+	void setDE(uint32_t value);
+	void setHL(uint32_t value);
+
 private:
 	uint32_t pcRead();
 	uint32_t pcRead16() { return pcRead() | (pcRead() << 8); }
@@ -67,9 +133,8 @@ private:
 	void ffWrite(uint32_t address, uint32_t value);
 	uint32_t ffRead(uint32_t address);
 
-	uint32_t bc() const { return m_b << 8 | m_c; }
-	uint32_t de() const { return m_b << 8 | m_c; }
-	uint32_t hl() const { return m_b << 8 | m_c; }
+	bool isCarry(uint32_t limit_bit, uint32_t first, uint32_t second, uint32_t third = 0x0);
+	bool isCarrySubtraction(uint32_t limit_bit, uint32_t lhs, uint32_t rhs, uint32_t rhs_extra = 0x0);
 
 	// Registers
 	uint32_t m_a { 0 };  // Accumulator
@@ -87,6 +152,14 @@ private:
 	uint32_t m_nf { 0 };  // Subtraction flag (BCD)
 	uint32_t m_hf { 0 };  // Half Carry flag (BCD)
 	uint32_t m_cf { 0 };  // Carry flag
+	uint32_t m_ime { 0 }; // Interrupt Master Enable flag
 
+	bool m_should_enable_ime { 0 };
 	int8_t m_wait_cycles { 0 };
 };
+
+template<>
+struct ruc::format::Formatter<CPU> : Formatter<uint32_t> {
+	void parse(Parser& parser);
+	void format(Builder& builder, const CPU& value) const;
+};

src/dma.cpp

@@ -1,6 +1,5 @@
 /*
  * Copyright (C) 2022 Riyyi
- * Copyright (C) 2022 Th3FrankXD
  *
  * SPDX-License-Identifier: MIT
  */

src/dma.h

@@ -1,6 +1,5 @@
 /*
  * Copyright (C) 2022 Riyyi
- * Copyright (C) 2022 Th3FrankXD
  *
  * SPDX-License-Identifier: MIT
  */

src/emu.cpp

@@ -12,6 +12,8 @@
 
 #include "cpu.h"
 #include "emu.h"
+#include "loader.h"
+#include "ruc/format/log.h"
 #include "ruc/format/print.h"
 #include "ruc/meta/assert.h"
 
@@ -37,7 +39,7 @@ void Emu::update()
 	}
 }
 
-void Emu::addProcessingUnit(std::string_view name, ProcessingUnit* processing_unit)
+void Emu::addProcessingUnit(std::string_view name, std::shared_ptr<ProcessingUnit> processing_unit)
 {
 	m_processing_units.emplace(name, processing_unit);
 }
@@ -55,8 +57,23 @@ void Emu::addMemorySpace(std::string_view name, uint32_t start_address, uint32_t
 	m_memory_spaces.emplace(name, std::move(memory_space));
 }
 
+void Emu::removeMemorySpace(std::string_view name)
+{
+	m_memory_spaces.erase(name);
+}
+
 void Emu::writeMemory(uint32_t address, uint32_t value)
 {
+	// Bail if the CPU tries to write to a read-only address
+	switch (address) {
+	case 0xff44:
+		ruc::error("writing to read-only address: {:#06x}", address);
+		VERIFY_NOT_REACHED();
+		break;
+	default:
+		break;
+	}
+
 	for (auto& memory_space : m_memory_spaces) {
 		auto& memory = memory_space.second;
 		if (address >= memory.start_address && address <= memory.end_address) {
@@ -65,23 +82,52 @@ void Emu::writeMemory(uint32_t address, uint32_t value)
 				writeMemory(address + (0xe000 - 0xc000), value);
 			}
 
-			memory.memory[memory.active_bank][address] = value;
+			memory.memory[memory.active_bank][address - memory.start_address] = value;
+
+			if (address == 0xff50) {
+				print("DISABLING BOOTROM\n");
+				Loader::the().disableBootrom();
+			}
+
+			// Write serial data from linkport I/O, used for blargg's test ROMs
+			if (address == 0xff02 && value == 0x81) {
+				uint32_t data = readMemory(0xff01);
+				print("{:c}", (data >= 58 && data <= 64) ? data + 7 : data);
+			}
+
 			return;
 		}
 	}
 
+	ruc::error("writing into address '{:#06x}' which is not in a memory space!", address);
+
 	VERIFY_NOT_REACHED();
 }
 
 uint32_t Emu::readMemory(uint32_t address) const
 {
+	switch (address) {
+	case 0xff44:
+		return *m_processing_units.at("PPU")->sharedRegister("LY");
+	default:
+		break;
+	};
+
 	for (const auto& memory_space : m_memory_spaces) {
 		const auto& memory = memory_space.second;
 		if (address >= memory.start_address && address <= memory.end_address) {
-			return memory.memory[memory.active_bank][address];
+			return memory.memory[memory.active_bank][address - memory.start_address];
 		}
 	}
 
+	// When trying to access the cartridge header
+	if (address >= 0x100 && address <= 0x14f) {
+		ruc::error("no cartridge loaded!");
+	}
+	else {
+		ruc::error("reading from address '{:#06x}' which is not in a memory space!", address);
+	}
+
 	VERIFY_NOT_REACHED();
 	return 0;
 }

src/emu.h

@@ -8,7 +8,7 @@
 #pragma once
 
 #include <cstdint> // uint32_t
-#include <string>
+#include <memory>  // std::shared_ptr
 #include <string_view>
 #include <unordered_map>
 #include <vector>
@@ -30,21 +30,30 @@ class Emu final : public ruc::Singleton<Emu> {
 public:
 	Emu(s) {}
 
+	enum Mode : uint8_t {
+		DMG, // Game Boy
+		CGB, // Game Boy Color
+	};
+
 	void init(uint32_t frequency);
 
 	void update();
 
-	void addProcessingUnit(std::string_view name, ProcessingUnit* processing_unit);
+	void addProcessingUnit(std::string_view name, std::shared_ptr<ProcessingUnit> processing_unit);
 	void addMemorySpace(std::string_view name, uint32_t start_address, uint32_t end_address, uint32_t amount_of_banks = 1);
+	void removeMemorySpace(std::string_view name);
 
 	void writeMemory(uint32_t address, uint32_t value);
 	uint32_t readMemory(uint32_t address) const;
 
 	// -------------------------------------
 
-	ProcessingUnit* processingUnit(std::string_view name) const { return m_processing_units.at(name); }
+	Mode mode() const { return m_mode; }
+	std::shared_ptr<ProcessingUnit> processingUnit(std::string_view name) const { return m_processing_units.at(name); }
+	MemorySpace memorySpace(std::string_view name) { return m_memory_spaces[name]; }
 
 private:
+	Mode m_mode { Mode::DMG };
 	uint32_t m_frequency { 0 };
 	double m_timestep { 0 };
 	uint32_t m_cycle { 0 };
@@ -53,6 +62,6 @@ private:
 
 	ruc::Timer m_timer;
 
-	std::unordered_map<std::string_view, ProcessingUnit*> m_processing_units;
+	std::unordered_map<std::string_view, std::shared_ptr<ProcessingUnit>> m_processing_units;
 	std::unordered_map<std::string_view, MemorySpace> m_memory_spaces;
 };

src/loader.cpp

@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2022 Riyyi
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#include <cstddef> // size_t
+#include <cstdint> // uint32_t
+#include <memory>  // std::make_shared
+
+#include "cpu.h"
+#include "emu.h"
+#include "loader.h"
+#include "ppu.h"
+#include "ruc/file.h"
+#include "ruc/format/print.h"
+
+void Loader::loadRom(std::string_view rom_path)
+{
+	if (!rom_path.empty()) {
+		m_rom_data = ruc::File(rom_path).data();
+	}
+
+	init();
+}
+
+void Loader::disableBootrom()
+{
+	Emu::the().removeMemorySpace("BOOTROM1");
+	Emu::the().removeMemorySpace("CARTHEADER");
+	Emu::the().removeMemorySpace("BOOTROM2");
+
+	// Load cartridge bank 0
+	Emu::the().addMemorySpace("CARTROM1", 0x0000, 0x3fff); // 16KiB
+	for (size_t i = 0x0000; i <= 0x3fff; ++i) {
+		Emu::the().writeMemory(i, m_rom_data[i]);
+	}
+}
+
+// -----------------------------------------
+
+void Loader::init()
+{
+	destroy();
+
+	Emu::the().init(4000000);
+
+	auto cpu = std::make_shared<CPU>(4000000);
+	auto ppu = std::make_shared<PPU>(4000000);
+
+	Emu::the().addProcessingUnit("CPU", cpu);
+	Emu::the().addProcessingUnit("PPU", ppu);
+
+	// https://gbdev.io/pandocs/Memory_Map.html
+	// https://gbdev.io/pandocs/Power_Up_Sequence.html
+	Emu::the().addMemorySpace("BOOTROM1", 0x0000, 0x00ff); // 256B
+	loadCartridgeHeader();
+	Emu::the().addMemorySpace("BOOTROM2", 0x0200, 0x08ff); // 1792B
+	loadCartridgeBanks();
+	Emu::the().addMemorySpace("VRAM", 0x8000, 0x9fff, 2);    // 8KiB * 2 banks
+	Emu::the().addMemorySpace("CARTRAM", 0xa000, 0xbfff, 1); // 8KiB * ? banks, if any
+	Emu::the().addMemorySpace("WRAM1", 0xc000, 0xcfff);      // 4 KiB, Work RAM
+	Emu::the().addMemorySpace("WRAM2", 0xd000, 0xdfff, 7);   // 4 KiB * 7 banks, Work RAM
+	Emu::the().addMemorySpace("ECHORAM", 0xe000, 0xfdff);    // 7680B, Mirror of 0xc000~0xddff
+	Emu::the().addMemorySpace("OAM", 0xfe00, 0xfe9f);        // 160B, Object Attribute Memory (VRAM Sprite Attribute Table)
+	Emu::the().addMemorySpace("Not Usable", 0xfea0, 0xfeff); // 96B, Nintendo probibits this area
+	Emu::the().addMemorySpace("IO", 0xff00, 0xff7f);         // 128B, I/O Registers
+	Emu::the().addMemorySpace("HRAM", 0xff80, 0xfffe);       // 127B, High RAM (CPU cache)
+	Emu::the().addMemorySpace("IE", 0xffff, 0xffff);         // 1B, Interrupt Enable register
+
+	// Load bootrom
+	auto bootrom = ruc::File(m_bootrom_path).data();
+	for (size_t i = 0; i < bootrom.length(); ++i) {
+		// Skip cartridge header memory range
+		if (i >= 0x0100 && i <= 0x01ff) {
+			continue;
+		}
+
+		Emu::the().writeMemory(i, bootrom[i]);
+	}
+}
+
+void Loader::destroy()
+{
+	Emu::destroy();
+}
+
+void Loader::loadCartridgeHeader()
+{
+	if (m_rom_data.empty()) {
+		return;
+	}
+
+	Emu::the().addMemorySpace("CARTHEADER", 0x100, 0x14f); // 80B
+
+	for (size_t i = 0x0100; i <= 0x014f; ++i) {
+		Emu::the().writeMemory(i, m_rom_data[i]);
+	}
+}
+
+void Loader::loadCartridgeBanks()
+{
+	if (m_rom_data.empty()) {
+		return;
+	}
+
+	uint32_t rom_size = 32 * 1024 * (1 << m_rom_data[0x0148]);
+	uint32_t rom_banks = rom_size / (16 * 1024) - 1;
+	Emu::the().addMemorySpace("CARTROM2", 0x4000, 0x7fff, rom_banks); // 16KiB * banks
+
+	// Load cartridge bank 1~NN
+	auto rom_memory_spaces = Emu::the().memorySpace("CARTROM2");
+	for (size_t i = 0; i < rom_banks; ++i) {
+		for (size_t i = 0x4000; i <= 0x7fff; ++i) {
+			Emu::the().writeMemory(i, m_rom_data[i]);
+		}
+		rom_memory_spaces.active_bank += 1;
+	}
+	rom_memory_spaces.active_bank = 0;
+}

src/loader.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2022 Riyyi
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#pragma once
+
+#include <string>
+#include <string_view>
+
+#include "ruc/singleton.h"
+
+class Loader final : public ruc::Singleton<Loader> {
+public:
+	Loader(s) {}
+
+	void loadRom(std::string_view rom_path);
+	void disableBootrom();
+
+	void setBootromPath(std::string_view bootrom_path) { m_bootrom_path = bootrom_path; }
+
+private:
+	void init();
+	void destroy();
+
+	void loadCartridgeHeader();
+	void loadCartridgeBanks();
+
+	std::string_view m_bootrom_path;
+	std::string m_rom_data;
+};

src/main.cpp

@@ -5,63 +5,56 @@
  * SPDX-License-Identifier: MIT
  */
 
-#include "cpu.h"
-#include "emu.h"
+#include <string_view>
+
+#include "inferno.h"
+#include "inferno/entrypoint.h"
 #include "ppu.h"
-#include "ruc/file.h"
+#include "ruc/argparser.h"
 #include "ruc/format/print.h"
 #include "ruc/timer.h"
 
-int main(int argc, char* argv[])
+#include "emu.h"
+#include "loader.h"
+
+class GarbAGE final : public Inferno::Application {
+public:
+	GarbAGE(int argc, char* argv[])
+		: Application()
 	{
-	(void)argc;
-	(void)argv;
+		std::string_view bootrom_path = "gbc_bios.bin";
+		std::string_view rom_path;
 
-	ruc::Timer t;
+		ruc::ArgParser argParser;
+		argParser.addOption(bootrom_path, 'b', "bootrom", nullptr, nullptr, "", ruc::ArgParser::Required::Yes);
+		argParser.addOption(rom_path, 'r', "rom", nullptr, nullptr, "", ruc::ArgParser::Required::Yes);
+		argParser.parse(argc, argv);
 
-	print("{}ms\n", t.elapsedNanoseconds() / 1000000.0);
-
-	Emu::the().init(8000000);
-
-	CPU cpu(8000000);
-	PPU ppu(4000000);
-
-	Emu::the().addProcessingUnit("cpu", &cpu);
-	Emu::the().addProcessingUnit("ppu", &ppu);
-
-	// https://gbdev.io/pandocs/Memory_Map.html
-	// https://gbdev.io/pandocs/Power_Up_Sequence.html
-	Emu::the().addMemorySpace("BOOTROM1", 0x0000, 0x00ff);   // 256B
-	Emu::the().addMemorySpace("BOOTROM2", 0x0200, 0x08ff);   // 1792B
-	Emu::the().addMemorySpace("VRAM", 0x8000, 0x9fff, 2);    // 8KiB * 2 banks
-	Emu::the().addMemorySpace("CARDRAM", 0xa000, 0xbfff, 1); // 8KiB * ? banks, if any
-	Emu::the().addMemorySpace("WRAM1", 0xc000, 0xcfff);      // 4 KiB, Work RAM
-	Emu::the().addMemorySpace("WRAM2", 0xd000, 0xdfff, 7);   // 4 KiB * 7 banks, Work RAM
-	Emu::the().addMemorySpace("ECHORAM", 0xe000, 0xfdff);    // 7680B, Mirror of 0xc000~0xddff
-	Emu::the().addMemorySpace("OAM", 0xfe00, 0xfe9f);        // 160B, Object Attribute Memory (VRAM Sprite Attribute Table)
-	Emu::the().addMemorySpace("Not Usable", 0xfea0, 0xfeff); // 96B, Nintendo probibits this area
-	Emu::the().addMemorySpace("IO", 0xff00, 0xff7f);         // 128B, I/O Registers
-	Emu::the().addMemorySpace("HRAM", 0xff80, 0xfffe);       // 127B, High RAM (CPU cache)
-	Emu::the().addMemorySpace("IE", 0xffff, 0xffff);         // 1B, Interrupt Enable register
-
-	// Load bootrom
-	auto bootrom = ruc::File("gbc_bios.bin").data();
-	for (size_t i = 0; i < bootrom.length(); ++i) {
-		// Skip cartridge header memory range
-		if (i >= 0x0100 && i <= 0x01ff) {
-			continue;
+		Loader::the().setBootromPath(bootrom_path);
+		Loader::the().loadRom(rom_path);
 	}
 
-		Emu::the().writeMemory(i, bootrom[i]);
+	~GarbAGE()
+	{
 	}
 
-	// Get shared register
-	print("{}\n", *Emu::the().processingUnit("cpu")->sharedRegister("a"));
-	print("{}\n", *Emu::the().processingUnit("cpu")->sharedRegister("b"));
-
-	while (true) {
+	void update() override
+	{
+		// 154 scanlines * 456 cycles = 70224 cycles per frame
+		for (int i = 0; i < (144 * 456 + 10 * 456); ++i) {
 			Emu::the().update();
 		}
-
-	return 0;
+	}
+
+	void render() override
+	{
+		auto* ppu = static_cast<PPU*>(Emu::the().processingUnit("PPU").get());
+		ppu->render();
+	}
+};
+
+Inferno::Application* Inferno::createApplication(int argc, char* argv[])
+{
+	GarbAGE* gameboy = new GarbAGE(argc, argv);
+	return gameboy;
 }

src/ppu.cpp

@@ -5,13 +5,28 @@
  * SPDX-License-Identifier: MIT
  */
 
-#include "ppu.h"
-#include "ruc/format/print.h"
-#include <iostream>
+#include <cstdint> // uint8_t, uint16_t, uint32_t
+#include <memory>  // std::make_shared
 
-PPU ::PPU(unsigned int frequency)
+#include "glm/ext/vector_float3.hpp" // glm::vec3
+#include "glm/ext/vector_float4.hpp" // glm::vec4
+#include "inferno/application.h"
+#include "inferno/component/spritecomponent.h"
+#include "inferno/component/transformcomponent.h"
+#include "inferno/scene/scene.h"
+#include "ruc/format/print.h"
+
+#include "emu.h"
+#include "ppu.h"
+#include "ruc/meta/assert.h"
+
+PPU::PPU(uint32_t frequency)
 	: ProcessingUnit(frequency)
 {
+	m_shared_registers.emplace("LY", &m_lcd_y_coordinate);
+
+	auto& scene = Inferno::Application::the().scene();
+	m_entity = scene.findEntity("Screen");
 }
 
 PPU::~PPU()
@@ -20,5 +35,268 @@ PPU ::~PPU()
 
 void PPU::update()
 {
-	// print("ppu update\n");
+	LCDC lcd_control = static_cast<LCDC>(Emu::the().readMemory(0xff40));
+	if (!(lcd_control & LCDC::LCDandPPUEnable)) {
+		return;
+	}
+
+	// print("PPU update\n");
+
+	m_clocks_into_frame++;
+
+	switch (m_state) {
+	case State::OAMSearch:
+		// OAM logic goes here..
+
+		if (m_clocks_into_frame % 80 == 0) {
+			// Reset FIFO
+			m_pixel_fifo = {};
+
+			m_state = State::PixelTransfer;
+		}
+		break;
+	case State::PixelTransfer:
+		updatePixelFifo();
+
+		if (m_lcd_x_coordinate == 160) {
+			m_lcd_x_coordinate = 0;
+			m_state = State::HBlank;
+		}
+		break;
+	case State::HBlank:
+		// H-Blank logic goes here..
+
+		if (m_clocks_into_frame % (80 + 172 + 204) == 0) {
+			m_lcd_y_coordinate++;
+			if (m_lcd_y_coordinate == 144) {
+				m_state = State::VBlank;
+			}
+			else {
+				m_state = State::OAMSearch;
+			}
+		}
+		break;
+	case State::VBlank:
+		// V-Blank logic goes here..
+
+		if (m_clocks_into_frame % (80 + 172 + 204) == 0) {
+			m_lcd_y_coordinate++;
+			if (m_lcd_y_coordinate == 154) {
+				resetFrame();
+			}
+		}
+
+		break;
+	default:
+		VERIFY_NOT_REACHED();
+	};
+}
+
+void PPU::render()
+{
+	LCDC lcd_control = static_cast<LCDC>(Emu::the().readMemory(0xff40));
+
+	if (!(lcd_control & LCDC::BGandWindowEnable)) {
+		// When Bit 0 is cleared, both background and window become blank (white)
+		auto pixel = getPixelColor(0, Palette::BGP);
+		for (size_t i = 0; i < m_screen.size(); i += 3) {
+			m_screen[i + 0] = pixel[0];
+			m_screen[i + 1] = pixel[1];
+			m_screen[i + 2] = pixel[2];
+		}
+	}
+
+	auto& scene = Inferno::Application::the().scene();
+	auto texture = std::make_shared<Inferno::Texture>(m_screen.data(), SCREEN_WIDTH, SCREEN_HEIGHT, FORMAT_SIZE);
+	scene.removeComponent<Inferno::SpriteComponent>(m_entity);
+	scene.addComponent<Inferno::SpriteComponent>(m_entity, glm::vec4 { 1.0f }, texture);
+}
+
+void PPU::resetFrame()
+{
+	m_state = State::OAMSearch;
+	m_clocks_into_frame = 0;
+	m_lcd_x_coordinate = 0;
+	m_lcd_y_coordinate = 0;
+}
+
+// -----------------------------------------
+
+uint32_t PPU::getBgTileDataAddress(uint8_t tile_index)
+{
+	// https://gbdev.io/pandocs/Tile_Data.html
+	switch (m_pixel_fifo.tile_data_address) {
+	case 0x8000:
+		// 0x8000-0x8fff: index   0 => 255
+		return m_pixel_fifo.tile_data_address + (tile_index * TILE_SIZE); // Each tile is 16 bytes
+	case 0x8800:
+		// 0x8800-0x8fff: index 128 => 255 (or -128 => -1)
+		// 0x9000-0x97ff: index   0 => 127
+		if (tile_index <= 127) {
+			return m_pixel_fifo.tile_data_address + 0x800 + (tile_index * TILE_SIZE); // Each tile is 16 bytes
+		}
+		else {
+			return m_pixel_fifo.tile_data_address + ((tile_index - 128) * TILE_SIZE); // Each tile is 16 bytes
+		}
+	default:
+		VERIFY_NOT_REACHED();
+		return 0;
+	};
+};
+
+std::array<uint8_t, 3> PPU::getPixelColor(uint8_t color_index, Palette palette)
+{
+	VERIFY(color_index < 4, "trying to fetch invalid color index '{}'", color_index);
+
+	switch (Emu::the().mode()) {
+	case Emu::Mode::DMG: {
+		uint8_t palette_data = Emu::the().readMemory(palette) & 0xff;
+		uint8_t palette_value = palette_data >> (color_index * 2) & 0x3;
+		switch (palette_value) {
+		case 0:
+			return { 200, 199, 168 };
+		case 1:
+			return { 160, 160, 136 };
+		case 2:
+			return { 104, 104, 80 };
+		case 3:
+			return { 39, 40, 24 };
+		default:
+			VERIFY_NOT_REACHED();
+		};
+	}
+	case Emu::Mode::CGB:
+		VERIFY_NOT_REACHED();
+	default:
+		VERIFY_NOT_REACHED();
+	}
+
+	return {};
+}
+
+void PPU::updatePixelFifo()
+{
+	switch (m_pixel_fifo.state) {
+	case PixelFifo::State::TileIndex:
+		tileIndex();
+		break;
+	case PixelFifo::State::TileDataLow:
+		tileDataLow();
+		break;
+	case PixelFifo::State::TileDataHigh:
+		tileDataHigh();
+		break;
+	case PixelFifo::State::Sleep:
+		sleep();
+		break;
+	case PixelFifo::State::Push:
+		pushFifo();
+		break;
+	default:
+		VERIFY_NOT_REACHED();
+	};
+
+	pushPixel();
+}
+
+void PPU::tileIndex()
+{
+	if (!m_pixel_fifo.step) {
+		m_pixel_fifo.step = true;
+	}
+	else {
+		m_pixel_fifo.step = false;
+		m_pixel_fifo.state = PixelFifo::State::TileDataLow;
+
+		LCDC lcd_control = static_cast<LCDC>(Emu::the().readMemory(0xff40));
+
+		// Tile map
+		uint32_t bg_tile_map_address = (lcd_control & LCDC::BGTileMapArea) ? 0x9c00 : 0x9800;
+		// uint32_t window_tile_map_address = (lcd_control & LCDC::WindowTileMapArea) ? 0x9c00 : 0x9800;
+
+		// Tile data
+		m_pixel_fifo.tile_data_address = (lcd_control & LCDC::BGandWindowTileDataArea) ? 0x8000 : 0x8800;
+
+		// Viewport
+		// https://gbdev.io/pandocs/Scrolling.html#mid-frame-behavior
+		m_pixel_fifo.viewport_x = Emu::the().readMemory(0xff43); // TODO: only read lower 3-bits at beginning of scanline
+		m_pixel_fifo.viewport_y = Emu::the().readMemory(0xff42);
+
+		// Read the tile map index
+		uint16_t offset = (((m_pixel_fifo.viewport_y + m_lcd_y_coordinate) / TILE_HEIGHT) * 32)
+		                  + ((m_pixel_fifo.viewport_x + m_pixel_fifo.x_coordinate) / TILE_WIDTH);
+		m_pixel_fifo.x_coordinate += 8;
+		m_pixel_fifo.tile_index = Emu::the().readMemory(bg_tile_map_address + offset);
+
+		// Set the tile line we're currently on
+		m_pixel_fifo.tile_line = (m_pixel_fifo.viewport_y + m_lcd_y_coordinate) % TILE_HEIGHT;
+	}
+}
+
+void PPU::tileDataLow()
+{
+	if (!m_pixel_fifo.step) {
+		m_pixel_fifo.step = true;
+	}
+	else {
+		m_pixel_fifo.step = false;
+		m_pixel_fifo.state = PixelFifo::State::TileDataHigh;
+
+		// Read tile data
+		m_pixel_fifo.pixels_lsb = Emu::the().readMemory(
+			getBgTileDataAddress(m_pixel_fifo.tile_index)
+			+ m_pixel_fifo.tile_line * 2); // Each tile line is 2 bytes
+	}
+}
+
+void PPU::tileDataHigh()
+{
+	if (!m_pixel_fifo.step) {
+		m_pixel_fifo.step = true;
+	}
+	else {
+		m_pixel_fifo.step = false;
+		m_pixel_fifo.state = PixelFifo::State::Sleep;
+
+		// Read tile data
+		m_pixel_fifo.pixels_msb = Emu::the().readMemory(
+			getBgTileDataAddress(m_pixel_fifo.tile_index)
+			+ m_pixel_fifo.tile_line * 2 // Each tile line is 2 bytes
+			+ 1);
+	}
+}
+
+void PPU::sleep()
+{
+	if (m_pixel_fifo.background.size() <= TILE_WIDTH + 1) {
+		m_pixel_fifo.state = PixelFifo::State::Push;
+	}
+}
+
+void PPU::pushFifo()
+{
+	m_pixel_fifo.state = PixelFifo::State::TileIndex;
+
+	for (uint8_t i = 0; i < TILE_WIDTH; ++i) {
+		uint8_t color_index = (m_pixel_fifo.pixels_lsb >> (7 - i)
+		                       | ((m_pixel_fifo.pixels_msb >> (7 - i)) << 1))
+		                      & 0x3;
+		m_pixel_fifo.background.push({ color_index, Palette::BGP });
+	}
+}
+
+void PPU::pushPixel()
+{
+	// The pixel FIFO needs to contain more than 8 pixels to shift one out
+	if (m_pixel_fifo.background.size() > 8) {
+		auto pixel = m_pixel_fifo.background.front();
+		m_pixel_fifo.background.pop();
+
+		uint32_t index = (m_lcd_y_coordinate * SCREEN_WIDTH + m_lcd_x_coordinate) * FORMAT_SIZE;
+		auto color = getPixelColor(pixel.first, pixel.second);
+		m_screen[index + 0] = color[0];
+		m_screen[index + 1] = color[1];
+		m_screen[index + 2] = color[2];
+		m_lcd_x_coordinate++;
+	}
 }

src/ppu.h

@@ -7,12 +7,103 @@
 
 #pragma once
 
+#include <array>
+#include <cstdint> // uint8_t, uint16_t, uint32_t
+#include <queue>
+#include <utility> // std::pair
+
+#include "ruc/meta/core.h"
+
 #include "processing-unit.h"
 
+#define SCREEN_WIDTH 160
+#define SCREEN_HEIGHT 144
+#define FORMAT_SIZE 3
+#define TILE_WIDTH 8
+#define TILE_HEIGHT 8
+#define TILE_SIZE 16
+
 class PPU final : public ProcessingUnit {
 public:
-	PPU(unsigned int frequency);
-	virtual ~PPU();
+	PPU(uint32_t frequency);
+	~PPU();
 
-	virtual void update() override;
+	enum LCDC : uint8_t {
+		None = 0,
+		BGandWindowEnable = BIT(0),
+		OBJEnable = BIT(1),
+		OBJSize = BIT(2),                 // 0 = 8x8, 1 = 8x16
+		BGTileMapArea = BIT(3),           // 0 = 0x9800-9bff, 1 = 0x9c00-9fff
+		BGandWindowTileDataArea = BIT(4), // 0 = 0x8800-97ff, 1 = 0x8000-8fff
+		WindowEnable = BIT(5),            //
+		WindowTileMapArea = BIT(6),       // 0 = 0x9800-9bff, 1 = 0x9c00-9fff
+		LCDandPPUEnable = BIT(7),
+	};
+
+	enum State : uint8_t {
+		HBlank = 0,
+		VBlank = 1,
+		OAMSearch = 2,
+		PixelTransfer = 3,
+	};
+
+	enum Palette : uint16_t {
+		BGP = 0xff47,  // BG and Window palette
+		OBP0 = 0xff48, // OBJ palette 0
+		OBP1 = 0xff49, // OBJ palette 1
+	};
+
+	struct PixelFifo {
+		enum State : uint8_t {
+			TileIndex,
+			TileDataLow,
+			TileDataHigh,
+			Sleep,
+			Push,
+		};
+
+		State state { State::TileIndex };
+		bool step { false };
+		uint32_t tile_data_address { 0 };
+		uint8_t viewport_x { 0 };
+		uint8_t viewport_y { 0 };
+		uint8_t x_coordinate { 0 };
+		uint8_t tile_index { 0 };
+		uint8_t tile_line { 0 };
+		uint8_t pixels_lsb { 0 };
+		uint8_t pixels_msb { 0 };
+
+		using Fifo = std::queue<std::pair<uint8_t, Palette>>; // colorID, source
+
+		Fifo background;
+		Fifo oam;
+	};
+
+	void update() override;
+	void render();
+	void resetFrame();
+
+private:
+	uint32_t getBgTileDataAddress(uint8_t tile_index);
+	std::array<uint8_t, 3> getPixelColor(uint8_t color_index, Palette palette);
+
+	void updatePixelFifo();
+	void tileIndex();
+	void tileDataLow();
+	void tileDataHigh();
+	void sleep();
+	void pushFifo();
+	void pushPixel();
+
+	// -------------------------------------
+
+	State m_state { State::OAMSearch };
+	uint32_t m_clocks_into_frame { 0 };
+	uint32_t m_lcd_x_coordinate { 0 };
+	uint32_t m_lcd_y_coordinate { 0 }; // Note: includes V-Blank
+
+	PixelFifo m_pixel_fifo;
+
+	uint32_t m_entity { 0 };
+	std::array<uint8_t, SCREEN_WIDTH * SCREEN_HEIGHT * FORMAT_SIZE> m_screen;
 };

test/testcpu.cpp

@@ -0,0 +1,182 @@
+/*
+ * Copyright (C) 2022 Riyyi
+ *
+ * SPDX-License-Identifier: MIT
+ */
+
+#include <memory> // std::make_shared, std::shared_ptr
+#include <vector>
+
+#include "cpu.h"
+#include "emu.h"
+#include "macro.h"
+#include "testcase.h"
+#include "testsuite.h"
+
+struct CPUTest {
+	CPU cpu { 0 };
+
+	bool isCarry(uint32_t limit_bit, uint32_t first, uint32_t second, uint32_t third = 0x0)
+	{
+		return cpu.isCarry(limit_bit, first, second, third);
+	}
+
+	bool isCarrySubtraction(uint32_t limit_bit, uint32_t lhs, uint32_t rhs, uint32_t rhs_extra = 0x0)
+	{
+		return cpu.isCarrySubtraction(limit_bit, lhs, rhs, rhs_extra);
+	}
+};
+
+std::shared_ptr<CPU> runCPUTest(std::vector<uint8_t> test)
+{
+	auto cpu = std::make_shared<CPU>(4000000);
+
+	Emu::the().destroy();
+	Emu::the().init(8000000);
+	Emu::the().addProcessingUnit("cpu", cpu);
+	Emu::the().addMemorySpace("FULL", 0x0000, 0xffff);
+
+	// Load the test
+	for (size_t i = 0; i < test.size(); ++i) {
+		Emu::the().writeMemory(i, test[i]);
+	}
+
+	// Run the test
+	while (cpu->pc() < test.size()) {
+		Emu::the().update();
+	}
+
+	return cpu;
+}
+
+// -----------------------------------------
+
+TEST_CASE(CPUIsCarry)
+{
+	CPUTest test;
+
+	// 8-bit Half-carry false
+
+	EXPECT(test.isCarry(0xf, 56, 17) == false);
+
+	EXPECT(test.isCarrySubtraction(0xf, 136, 1) == false);
+	EXPECT(test.isCarrySubtraction(0xf, 219, 20) == false);
+	EXPECT(test.isCarrySubtraction(0xf, 250, 20) == false);
+
+	// 8-bit Half-carry true
+
+	EXPECT(test.isCarry(0xf, 46, 34) == true);
+	EXPECT(test.isCarry(0xf, 62, 34) == true);
+
+	EXPECT(test.isCarrySubtraction(0xf, 16, 1) == true);
+	EXPECT(test.isCarrySubtraction(0xf, 32, 1) == true);
+	EXPECT(test.isCarrySubtraction(0xf, 144, 1) == true);
+	EXPECT(test.isCarrySubtraction(0xf, 211, 20) == true);
+
+	// 8-bit Full carry false
+
+	EXPECT(test.isCarry(0xff, 254, 1) == false);
+
+	// 8-bit Full carry true
+
+	EXPECT(test.isCarry(0xff, 254, 2) == true);
+}
+
+TEST_CASE(CPUAddPlusCarry)
+{
+	std::shared_ptr<CPU> cpu(0);
+
+	// ADC A,E
+
+	std::vector<uint8_t> adc_r8 = {
+		// clang-format off
+		0x3e, 0xe1,       // LD A,i8
+		0x1e, 0x0f,       // LD E,i8
+		0x37,             // SCF
+		0x8b,             // ADC A,E
+		// clang-format on
+	};
+	cpu = runCPUTest(adc_r8);
+	EXPECT_EQ(cpu->a(), 0xf1);
+	EXPECT_EQ(cpu->zf(), 0x0);
+	EXPECT_EQ(cpu->nf(), 0x0);
+	EXPECT_EQ(cpu->hf(), 0x1);
+	EXPECT_EQ(cpu->cf(), 0x0);
+
+	// ADC A,i8
+
+	std::vector<uint8_t> adc_i8 = {
+		// clang-format off
+		0x3e, 0xe1,       // LD A,i8
+		0x37,             // SCF
+		0xce, 0x3b,       // ADC A,i8
+		// clang-format on
+	};
+	cpu = runCPUTest(adc_i8);
+	EXPECT_EQ(cpu->a(), 0x1d);
+	EXPECT_EQ(cpu->zf(), 0x0);
+	EXPECT_EQ(cpu->nf(), 0x0);
+	EXPECT_EQ(cpu->hf(), 0x0);
+	EXPECT_EQ(cpu->cf(), 0x1);
+
+	// ADC A,(HL)
+
+	std::vector<uint8_t> adc_hl = {
+		// clang-format off
+		0x3e, 0xe1,       // LD A,i8
+		0x36, 0x1e,       // LD (HL),i8
+		0x37,             // SCF
+		0x8e,             // ADC A,(HL)
+		// clang-format on
+	};
+	cpu = runCPUTest(adc_hl);
+	EXPECT_EQ(cpu->a(), 0x0);
+	EXPECT_EQ(cpu->zf(), 0x1);
+	EXPECT_EQ(cpu->nf(), 0x0);
+	EXPECT_EQ(cpu->hf(), 0x1);
+	EXPECT_EQ(cpu->cf(), 0x1);
+}
+
+TEST_CASE(CPUSetStackPointer)
+{
+	std::vector<uint8_t> test = { 0x31, 0xfe, 0xff }; // LD SP,i16
+	auto cpu = runCPUTest(test);
+	EXPECT_EQ(cpu->sp(), 0xfffe);
+}
+
+TEST_CASE(CPUPushToStack)
+{
+	// PUSH BC
+
+	std::vector<uint8_t> push_bc = {
+		// clang-format off
+		0x31, 0xfe, 0xff, // LD SP,i16
+		0x01, 0xfc, 0xff, // LD BC,i16
+		0xc5,             // PUSH BC
+		// clang-format on
+	};
+	auto cpu = runCPUTest(push_bc);
+	EXPECT_EQ(cpu->bc(), 0xfffc);
+	EXPECT_EQ(cpu->sp(), 0xfffc);
+	EXPECT_EQ(Emu::the().readMemory(0xfffd), 0xff);
+	EXPECT_EQ(Emu::the().readMemory(0xfffc), 0xfc);
+}
+
+TEST_CASE(CPUPopFromStack)
+{
+	// POP BC
+
+	std::vector<uint8_t> pop_bc = {
+		// clang-format off
+		0x31, 0xfe, 0xff, // LD SP,i16
+		0x11, 0x5f, 0x3c, // LD DE,i16
+		0xd5,             // PUSH DE
+		0xc1,             // POP BC
+		// clang-format on
+	};
+	auto cpu = runCPUTest(pop_bc);
+	EXPECT_EQ(cpu->bc(), 0x3c5f);
+	EXPECT_EQ(cpu->sp(), 0xfffe);
+	EXPECT_EQ(Emu::the().readMemory(0xfffd), 0x3c);
+	EXPECT_EQ(Emu::the().readMemory(0xfffc), 0x5f);
+}

test/testthing.cpp

@@ -1,17 +0,0 @@
-/*
- * Copyright (C) 2022 Riyyi
- *
- * SPDX-License-Identifier: MIT
- */
-
-#include "macro.h"
-#include "testcase.h"
-#include "testsuite.h"
-
-// -----------------------------------------
-
-TEST_CASE(Thing)
-{
-	int a = 5;
-	EXPECT_EQ(a, 5);
-}